| --- Log opened Tue Feb 17 00:00:44 2015 | ||
| stekern | I just pushed my close to done lk port here: https://github.com/skristiansson/lk | 02:49 |
|---|---|---|
| stekern | the only thing left to do is to clean up the uart code | 02:51 |
| stekern | seems like there are about 5-6 different drivers for ns16550 in the tree | 02:52 |
| stekern | and I'm adding yet another | 02:52 |
| sheridp1 | Hello, I have a question about addressing in the open risc. I'm using the altor32, and see that the boot_vector is at h10000000 but the ram in the examples is only 24KB | 04:06 |
| sheridp1 | A lot of the example code has origin at 0x10000000; is there something I'm missing? with 24KB and 32bit wide, there would only be 6000 addresses | 04:07 |
| stekern | sheridp: is that altor32 example code you're referring to? | 05:59 |
| olofk | stekern: I see that you were also enlightened by the segfault PC question on the mailing list :) | 07:15 |
| olofk | And cool stuff with lk. That deserves a tweet and beer! | 07:16 |
| olofk | sheridp: Yes, it probably only uses a few hundred addresses, but the base address is 0x10000000, so it isn't using anything below that | 07:17 |
| olofk | antgreen: Have you considered using 32-bit buses for instruction and data? Most Wishbone peripherals are 32-bit so it would make it easier to use those straight away | 07:53 |
| _franck_ | olofk: I read your post on the forum about how to modify the core for tests | 08:35 |
| _franck_ | don't you think it's too complicate and we should find a way to make it easier ? | 08:36 |
| _franck_ | if you edit the core in ./build and don't use --force it should work right ? | 08:36 |
| olofk | _franck__: If you remove --force it won't rebuild the simulation model | 08:57 |
| olofk | And yes, it's a bit complicated, but not _that_ complicated. It's just to get the sources, copy the core file and remove the provider section | 08:58 |
| olofk | But if you have ideas for how to make it easier I'm interested in knowing | 08:58 |
| _franck_ | I don't for now :) | 09:01 |
| _franck_ | http://pasteboard.co/1bkOclnI.png | 09:31 |
| _franck_ | newlib toolchain compiled under MSYS2 | 09:31 |
| _franck_ | c++ disabled because it generates an internal gcc error while compiling | 09:32 |
| olofk | _franck__: Cool! I was actually wondering about windows support earlier today. I'm stuck on a Windows machine while my computer is on repair | 09:35 |
| olofk | It's a fucking nightmare to get things done | 09:35 |
| GeneralStupid | gcc is not a c++ compiler... is there something wrong with the makefiles? | 09:37 |
| _franck_ | gcc sources generate g++ if configured to do it | 09:38 |
| GeneralStupid | oh | 09:38 |
| wallento | _franck_: is the or1k stuff upstream in openocd? sorry, I somehow lost track of this.. | 10:01 |
| olofk | wallento: Yes. I used upstream 0.8.0 just a while ago | 10:43 |
| olofk | I would like to clean up the OpenRISC repos on github. OpenOCD would be a good candidate to remove if everything is upstream | 10:45 |
| olofk | Perhaps do the same thing with newlib once the next snapshot is released | 10:46 |
| olofk | If we are going to add stuff in the future, I guess we would clone upstream directly anyway | 10:46 |
| _franck_ | olofk: https://github.com/openrisc/openOCD/blob/master/src/target/or1k_jtag.c#L38 | 10:54 |
| _franck_ | ^ this is not upstream | 10:54 |
| _franck_ | but I could keep this in my own github | 10:54 |
| _franck_ | because I don't think I'll ever upstream it | 10:54 |
| stekern | olofk: I'll polish the port some more and then propose it 'upstream', I'm still ~a week here so hope to get it done before that | 10:55 |
| stekern | we're switching places tomorrow too, hopefully there is better internet connection there | 10:56 |
| stekern | .. just so you can plan for some more beer I mena | 10:56 |
| stekern | *mean | 10:56 |
| stekern | I just downed a chang in the sunset here, hence the typos ;) | 10:57 |
| stekern | _franck_: cool, reminds me that we should probably sync to 4.9.2 | 11:13 |
| olofk | stekern: Nice. The weather in this part of the world sucks right now so don't rush back here :) | 11:21 |
| olofk | _franck__: Is it only line 38 that is not upstream? | 11:21 |
| n0bawk | hello, I would like to try some external peripheral for or1ksim, however, I do not see it call the upcall interface. Would you please help me? | 11:46 |
| n0bawk | http://paste.ubuntu.com/10272088/ | 11:47 |
| n0bawk | this is my code | 11:47 |
| Akiraa | how difficult would it be to implement the "mass storage device" API (or equivalent) for a programmable device like 'banana pi' or olinuxino or similar boards? | 11:47 |
| n0bawk | and this is my sim.cfg: http://paste.ubuntu.com/10272119/ | 11:49 |
| Akiraa | I would be interested even in some useful keywords for search if you can help (implementing USB "mass storage device" from a linux box with USB-OTG) | 11:56 |
| wallento | olofk: I would keep a newlib repo on our organization. the docu can of course move to openrisc.github.io, but at the moment there are still a few features I plan to add. mainly MMU configuration | 12:18 |
| olofk | n0bawk: Sorry. Haven't used the or1ksim lib, but there should be others here who would know it better | 12:24 |
| olofk | wallento: Yes. That makes sense then if we have some kind of development planned for it | 12:25 |
| wallento | didn't really proceed with getting openocd to know there are two cores behind a tap | 12:26 |
| n0bawk | olofk: I am trying to model a SoC using TLM; however, I am not sure why the upcall does not work :( | 12:29 |
| n0bawk | I am trying to write data into the memory region defined in a generic section | 12:30 |
| olofk | n0bawk: I know that _franck__ did some experiments with embedding or1ksim in a verilator simulation. He might know | 12:31 |
| _franck_ | n0bawk: https://github.com/fjullien/or1ksim_lib_test | 12:33 |
| _franck_ | ^ it works for me | 12:33 |
| _franck_ | olofk: what is not upstream in our github openocd is the classic debug interface a.k.a Mohor | 12:33 |
| olofk | _franck__: Ah ok. Yeah. It could be good to have around, but the new interface should be enough to have upstream | 12:35 |
| n0bawk | _franck_: with your configuration it works, but with mine it does not | 12:38 |
| _franck_ | you have the same base address as the uart | 12:39 |
| _franck_ | 0x90000000 | 12:39 |
| _franck_ | try something else | 12:39 |
| _franck_ | oh it's disabled | 12:39 |
| n0bawk | hmmm, I tried with 0xA0000000 also | 12:40 |
| _franck_ | but try something else as a base address for the generic section, we never know | 12:40 |
| _franck_ | ah ok | 12:41 |
| _franck_ | well, shrink your cfg file to a minimum, then compare it to mine | 12:42 |
| n0bawk | so the problem is the configuration file | 12:44 |
| n0bawk | I disable other sections (left only the cpu and generic) and it works | 12:48 |
| n0bawk | If I enable the mc section, it will not work | 12:52 |
| _franck_ | never used this section, need to check the manual :) I can't help you | 12:55 |
| _franck_ | welcome to openrisc, now please open or1ksim source code and find why it doesn't work :) | 12:56 |
| rschmidlin | Hi, I have implemented the mor1k-generic design on an artix-7. Hello world worked fine. But when I try to turn on the caches I get an exception. Weirdly, the simulation runs to the end. Anyone has an idea of what might be going on? | 13:03 |
| rschmidlin | I was considering configuring MIG for my system and using what is available from the atlys system. But it seems that the mig interface has changed somewhat. | 13:05 |
| olofk | rschmidlin: Xilinx MIG is horrible. The interface is different between every version, every product family and dependning on if you generate verilog or VHDL | 13:13 |
| n0bawk | _franck_: thank you | 13:24 |
| rschmidlin | Olofk, a real pity. I still don't know why I get the exception on the block rams. :( | 14:08 |
| olofk | jeremybennett: You around? | 14:47 |
| olofk | rschmidlin: Are you using wb_ram as your memory? | 14:58 |
| Me1234_ | olofk: In this guide openocd is mentioned: http://kevinmehall.net/openrisc/guide/ | 15:09 |
| Me1234_ | Or is this older openocd | 15:09 |
| Me1234_ | olofk: ? | 15:09 |
| rschmidlin | Olofk, yes, ram_wb_b3.v | 15:19 |
| jeremybennett | olofk: I am | 15:20 |
| Me1234_ | olofk: I see that actually openocd works with orpsocv2, but the example timerled from orconf2013 repo loops somewhere around 0x00003544 in or1k_cache_init (). | 15:46 |
| Me1234_ | olofk: Wrong newlib? | 15:46 |
| Me1234_ | olofk: Orpsoc v2 works with old openocd, which i found on one of my virtual PCs, which, I think, has been downloaded from openrisc.net. | 16:03 |
| olofk | jeremybennett: Do you have any more of your fancy USB-to-UART adapters? | 17:04 |
| olofk | rschmidlin: ram_wb_b3 isn't really synthesisable | 17:04 |
| olofk | Me1234_: Ah yes. That's for a real target. I thought we were talking about simulations | 17:05 |
| olofk | rschmidlin: wb_ram should work though | 17:07 |
| olofk | Different things :) | 17:07 |
| olofk | Hmm... I got a feeling that we talked about this before | 17:07 |
| rschmidlin | Olofk, I don't know yet which part of it isn't. But I will take a look at it tomorrow. I'm also finally looking for a possibility to log to irc from work. | 17:17 |
| olofk | rschmidlin: I think you can use a web interface to connect if you can't connect directly | 17:51 |
| olofk | Me1234_: Looping in the cache init does sound wrong. Haven't got any explanation though | 17:59 |
| -!- julzmb_ is now known as julzmb | 18:20 | |
| Me1234_ | olofk: Looping in the cache init happens only with new openocd. | 18:29 |
| olofk | Me1234: What? Just changing the OpenOCD version? | 19:27 |
| Me1234 | olofk: Wait. I will check again. | 19:45 |
| Me1234 | olofk: I do not know. I cannot reproduce the error now. I will try later. I have no time | 19:49 |
| Me1234 | . | 19:49 |
| Me1234 | Now I have working linux booting from spi flash on de0_nano with orposc v2 | 19:50 |
| olofk | Me1234: That's good to know! SPI flash booting is one of the remaining things I haven't taken care of yet for the new OpenRISC systems | 19:57 |
| Me1234 | olofk: It is an old openrisc system: orpsoc v2. | 20:06 |
| olofk | Me1234: Yeah, but it's good to know that it's working there, so I don't start porting something that is broken :) | 20:09 |
| olofk | What the...? Downloaded a zip file from Spansion that should contain a verilog model. Inside the zip is a .exe file | 22:10 |
| olofk | I'm not going to compile Wine for this | 22:11 |
| olofk | Any Windows user around who can tell me what the exe in this archive does? http://www.spansion.com/Support/Lists/ProductModels/Attachments/14/S25FL032P_Verilog_VHDL.zip | 22:13 |
| olofk | Aha! Found it on Free Model Foundry instead | 22:18 |
| --- Log closed Wed Feb 18 00:00:46 2015 | ||
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