| --- Log opened Mon Feb 16 00:00:43 2015 | ||
| wallento | _franck_: did you have a look at the multicore openocd topic? | 09:42 |
|---|---|---|
| poke53282 | stekern: Nope, everything on my harddrive. | 09:58 |
| poke53282 | But the changes in the end were minor. Just take the repository from blueCmd. | 09:59 |
| poke53282 | You don't get anything new by using the newest QEMU version. | 09:59 |
| _franck_ | wallento: a loooong time ago. Long enough to forget everything I would have learnt | 10:46 |
| _franck_ | but I think it wasn't that hard | 10:46 |
| wallento | _franck_: thanks, I will have a look at it | 15:13 |
| Me1234 | Why does neither old orpsoc nor mor1kx-dev-env work with gdb, openocd even with timerled examlple from orconf 2013 repo, not to mention linux | 16:22 |
| Me1234 | Where can i get orpsoc v2 | 16:57 |
| Me1234 | ? | 16:57 |
| -!- Netsplit *.net <-> *.split quits: stekern, ysionneau, jonmasters | 17:25 | |
| Me1234 | found it, git is a good thing, yo can always revert changes you made. | 17:31 |
| -!- Netsplit over, joins: ysionneau, stekern, jonmasters | 17:31 | |
| olofk | Me1234: ORPSoCv2 used another way to interact with GDB than the current systems in orpsoc-cores | 17:48 |
| olofk | And I'm not sure about mor1kx-dev-env. That hasn't been maintained for quite a while | 17:48 |
| olofk | What the hell is gecko03? | 19:24 |
| olofk | Google gives me results from everything from Austrian childcare, motorbikes, German books and muslim news sites | 19:26 |
| olofk | ok, found it | 19:29 |
| olofk | Great. It uses MicroBlaze | 19:30 |
| olofk | wankers | 19:30 |
| olofk | _franck_: Your extra files FuseSoC patch is awesome btw. I have already found several places where I want to use it | 19:39 |
| Me1234 | olofk: you mean adv_debug_sys? | 20:08 |
| sheridp | Does anyone know how to embed an elf into BRAM for a Xilinx FPGA? I'm trying to replace the bootloader in AltOR32 | 20:11 |
| olofk | Me1234: Not really. In ORPSoCv2 we had a VPI module that implemented a GDB server and translated that to JTAG, so you connect GDB directly to that. The method we use now is that we have a a small VPI module that OpenOCD connects to with the jtag-vpi driver, so that we can reuse the GDB server from OpenOCD instead. Less code to maintain for us and more like the real hardware workflow | 20:21 |
| olofk | sheridp: I have done that with MicroBlaze ELF files, but in that case objdump could create the correct format directly. For AltOr32 I guess you need to create a bin file and then convert that to a format that the Xilinx tools can recognize. Then there's the step of actually loading it. Is it an option to use wb_ram instead? In that case I can help you with scripts that turns an assembly file into something that can be loaded into the boot RAM | 20:24 |
| olofk | But since you are using AltOr32 instead of mor1kx or or1200 I presume you want to keep it VHDL only. Is that right? | 20:25 |
| sheridp | wb_ram would be great. Actually I prefer verilog, and am not even really stuck on the altor32; I just need something that can fit into a spartan6 lx9 | 20:29 |
| olofk | sheridp: I have a half-finished port for the LX9 MicroBoard with mor1kx | 20:31 |
| sheridp | I see that on your github, is that up to date? | 20:33 |
| olofk | sheridp: I haven't done any work on it after I put it on github. IIRC I got the led_blink bootloader working, but since I never connected the Flash, I didn't run any software on it | 20:58 |
| olofk | I will probably work on it a bit in three weeks | 20:59 |
| olofk | And the first thing to do then will probably be to connect the Flash and port the SPI bootloader from ORPSoCv2 | 20:59 |
| sheridp | olofk:Thanks, I'm going to fork it and try to get it running on my system (a mojoV3) | 21:00 |
| olofk | Cool. Let me know if I can help you with anything | 21:01 |
| olofk | Will you use FuseSoC btw? | 21:01 |
| olofk | The Mojov3 looks nice | 21:02 |
| sheridp | olofk: Yes, I'm just finding out about fusesoc today, but I will try to figure it out | 21:02 |
| olofk | Don't hesitate to ask for help. It still has some rough edges... like no documentation whatsoever :) | 21:04 |
| sheridp | olofk: I think it's a pretty similar question that I had earlier, how does fusesoc get the elf file into the fpga config bit file? | 21:14 |
| olofk | sheridp: You convert an assembly files via a bin file to a file that the verilog $readmemh command can parse. Then you set the memfile paramter of wb_ram to your generated .vh file | 21:24 |
| olofk | Damn. I thought I had pushed my collection of tiny bootloaders to github. hmm... where are they | 21:26 |
| olofk | Oh well. I'll find it. | 21:27 |
| sheridp | with readmemh being in an initial block, does that get executed when you synthesize for actual hardware or only for simulation? | 21:27 |
| olofk | That works for synthesis as well. That method is actually part of the verilog substandard for syntheisizable RTL | 21:28 |
| sheridp | ah, excellent I did not realize that | 21:29 |
| olofk | It's pretty neat. The biggest problem I have had is that I haven't been able to write wb_ram in a way that it's vendor agnostic, maps well against FPGA resources and can be preloaded at the same time | 21:30 |
| olofk | So I intend to push a wb_rom to be used for bootloaders and drop the preinitialization from wb_ram, because it just won't work reliably on Altera devices | 21:32 |
| sheridp | How is the performance of wb_ram? Does having other peripherals on the bus slow execution? | 21:33 |
| olofk | It's very quick since it's just using small on-chip RAM. If you have a shared data/instruction bus it will probably be slowed down if you try to access some peripheral on the data bus and read instructions from wb_ram, but that shouldn't be an issue | 21:37 |
| olofk | You will most likely only execute a handful of instructions from it and then load a real application into your main RAM | 21:38 |
| sheridp | Oh I see, I thought the wb_ram was to serve as the main RAM | 21:39 |
| olofk | No. Just as a rewritable boot loader, or if you need a small superfast memory area | 21:39 |
| olofk | hmm... I can't see any RAM on the Mojov3 | 21:40 |
| sheridp | No there's not any. You have to add it externally | 21:43 |
| olofk | In that case it will be your main RAM as well, but you will only have at most ~70KB RAM | 21:43 |
| olofk | aha. I see the SDRAM shield now | 21:44 |
| olofk | I guess the intention is to run sw in the MCU instead, but what fun is that? :) | 21:47 |
| sheridp | Yes, its | 21:48 |
| sheridp | actually someone annoying because there is only a serial bus connecting the two | 21:48 |
| olofk | Every FPGA deserves to have an OpenRISC in it! | 21:48 |
| --- Log closed Tue Feb 17 00:00:44 2015 | ||
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