| --- Log opened Sun Apr 02 00:00:11 2017 | ||
| --- Log closed Sun Apr 02 00:30:49 2017 | ||
| --- Log opened Sun Apr 02 00:30:56 2017 | ||
| -!- Irssi: #openrisc: Total of 42 nicks [0 ops, 0 halfops, 0 voices, 42 normal] | 00:30 | |
| -!- Irssi: Join to #openrisc was synced in 25 secs | 00:31 | |
| shorne | reading through openocd code, it seems hard coded to only talk to one openrisc cpu | 03:16 |
|---|---|---|
| shorne | it has the logic to talk to the second, but doesnt use it | 03:16 |
| shorne | also the verilog in adv_debug_sys supports 2 cores | 03:17 |
| shorne | I am now looking into patch secondary cpu support into openocd, not sure if anyone else has tried before | 03:18 |
| shorne | juliusb: It looks like you worked on openocd, do you remember if its possible to get it to support multiple cpus? | 03:31 |
| shorne | I think I figured out how to do it... | 04:08 |
| shorne | openocd inits like this | 04:08 |
| shorne | 1. jtag newtap ... | 04:08 |
| shorne | 2. target create (for openrisc this also inits jtag serial port, registers, memory access) | 04:09 |
| shorne | 3. init (calls target init) | 04:09 |
| shorne | currently if you call (2 target create) a second time it doesnt work. I can add logic to not re init everything on second target create, and also look at coreid to redirect calls to the different cpus | 04:10 |
| mithro | Do the developers of https://github.com/f32c/f32c hang out around here much? | 22:41 |
| --- Log closed Mon Apr 03 00:00:12 2017 | ||
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