| --- Log opened Sat Apr 01 00:00:09 2017 | ||
| -!- ZipCPU_ is now known as ZipCPU | 07:46 | |
| ZipCPU | So ... for any one interested in the discussion, I'm slowly building a program to build FPGA designs. I mentioned this the other day on #librecores, but ... there's more folks here. | 17:46 |
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| ZipCPU | I'm hoping the program might use core files, but ... it's going to need some more information. | 17:46 |
| ZipCPU | My thoughts are ... a design consists of a bus master (or multiple), together with multiple peripherals. The code currently is focused on the wishbone bus. | 17:47 |
| ZipCPU | As written, it will build a bus and assign addresses to all peripherals, to include building some C++ .h and .cpp files describing the bus architecture as built. | 17:47 |
| ZipCPU | I'm still hoping to add LaTeX file tables for each peripheral, just ... not there yet. | 17:48 |
| ZipCPU | What's also not done yet (but in progress), is the collection of peripherals having interrupts that need assignment (my designs tend to have 3-programmable interrupt controllers each ...) | 17:48 |
| ZipCPU | and the collection of peripherals having scopes that (may) need assignment. | 17:49 |
| ZipCPU | Can anyone think of anything I'm missing? I've got I/O ports taken care of, a toplevel.v and Verilog synthesizable main.v taken care of. (Both have io port lists, io port declarations, variable declarations, wire passing, and then special logic per peripheral or bus master within them ...) | 17:50 |
| ZipCPU | Peripherals themselves are divided into four classes: 1) those that always have an output available on every clock (even before a read), 2) those that must decode the address to produce an output on any clock (example: reading one of several registers), | 17:51 |
| ZipCPU | 3) memory peripherals that need their information placed into a linker script, and ... 4) everything else that doesn't need or doesn't get those optimizations. | 17:52 |
| --- Log closed Sun Apr 02 00:00:11 2017 | ||
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