| --- Log opened Sun Apr 17 00:00:25 2016 | ||
| olofk | mithro: Did you have to override the FPGA tap ID? | 02:44 |
|---|---|---|
| mithro | olofk: yes | 03:40 |
| -!- Netsplit *.net <-> *.split quits: trem, sandeepkr__ | 03:56 | |
| -!- Netsplit *.net <-> *.split quits: wallento, robtaylor, simoncook | 03:57 | |
| -!- wallento_ is now known as wallento | 03:57 | |
| -!- Netsplit *.net <-> *.split quits: trem_ | 04:12 | |
| -!- Netsplit *.net <-> *.split quits: julzmb, Amadiro_ | 04:12 | |
| -!- Netsplit *.net <-> *.split quits: Empyrium, rokka, jeremybennett, olofk | 04:12 | |
| -!- Netsplit over, joins: trem_ | 04:27 | |
| -!- Empyrium_ is now known as Empyrium | 04:28 | |
| olofk_ | mithro: Would be good to write down how to do that in the tutorial | 04:51 |
| olofk_ | andrzejr: nexys4ddr_top seems to build now with some fixes to FuseSoC and the rmii_to_mii core | 06:44 |
| andrzejr | olofk_, cool. Did you check out a fresh nexys4ddr branch or switched to it from master? | 06:49 |
| andrzejr | both repos have diverged quite a bit recently. | 06:49 |
| olofk_ | Hmm... why would that be different? I cloned your repo and checked out the nexys4ddr branch | 06:54 |
| -!- olofk_ is now known as olofk | 06:54 | |
| olofk | Alright! Build is complete. Don't have any board to test it with though :) | 06:56 |
| olofk | One tiny thing left to do. Unfortunately this one seems to require some major rework in FuseSoC :/ | 07:07 |
| olofk | FuseSoC currently parses the IP-XACT file when it loads the .core file, but the file isn't there until we have fetched it | 07:09 |
| olofk | And I would like to only run fetch on demand | 07:11 |
| olofk | This could be solved by having a special case where we fetch the core if the .core file contains a IP-XACT file, but it couldn't be found in the core root | 07:13 |
| olofk | I'm just a bit worried that this might open up other problems. Don't know what though | 07:14 |
| olofk | ah fuck it. I'll try and see if that works | 07:14 |
| olofk | Ha! It works. That will be good enough for now | 07:22 |
| olofk | andrzejr: With the latest fixes to FuseSoC, it should work now with some minor changes to your .core files | 07:27 |
| olofk | Remove the patches dir from xilinx_mii_to_rmii and apply this patch http://f3067bc5bbce025b.paste.se/ | 07:28 |
| olofk | The resulting bit file of course untested | 07:28 |
| olofk | wallento: I reviewed your vivado backend | 07:47 |
| olofk | Haven't tested it yet though. Got a good example project that I can use without your naming stuff? | 07:48 |
| -!- Netsplit *.net <-> *.split quits: feddischson, simoncook, Amadiro | 11:30 | |
| wallento | olofk: unfortunately not | 11:33 |
| -!- Netsplit over, joins: Amadiro | 11:36 | |
| -!- Netsplit *.net <-> *.split quits: aburgess | 12:32 | |
| bandvig | andrzejr: mithro: which kind of JTAG cable do you use? | 12:53 |
| andrzejr | bandvig, I'm using an on-board (Nexys4) USB<->JTAG cable. | 12:57 |
| -!- Netsplit *.net <-> *.split quits: aburgess_ | 13:00 | |
| bandvig | andrzejr: Nexys4 is Digilent's product. A have another Digilent's board - Atlys. Atlys also has got on-board USB-JTAG. Do you think I could use it in the same way as on Nexys4? | 13:03 |
| -!- Netsplit over, joins: aburgess_ | 13:11 | |
| olofk | bandvig: Well, you're in luck. mithro just got that working yesterday :) | 13:30 |
| olofk | It works by flashing the USB-JTAG converter with a custom firmware that makes it imitate the Altera USB Blaster protocol towards the USB side. Then you need to instantiate a Xilinx BSCAN JTAG Tap in the FPGA | 13:31 |
| bandvig | olofk: I saw yesterday discussion, but I didn't recognize that I need to re-program on-board USB-JTAG converter. | 13:37 |
| bandvig | olofk: perhaps, I would prefer to by Xilinx's "Platform Cable USB" and connect directly to FPGA (by instance of appropriate BSCAN). The only thing I worry if "Platform Cable USB" could be accessible from CygWin. | 13:43 |
| andrzejr | bandvig, olofk, I didn't have to flash anything, just set some driver options in the openocd script. But I'm not sure if nexys4 and atlys use the same cable. | 13:46 |
| andrzejr | Worth trying: | 13:46 |
| andrzejr | https://github.com/andrzej-r/orpsoc-cores/blob/nexys4ddr/systems/nexys4ddr/nexys4ddr_top/sw/nexys4ddr.tcl | 13:47 |
| andrzejr | It's all about the 5 ftdi_layout* calls at the top of the script. | 13:48 |
| bandvig | andrzejr: did you perform some reverse engeneering of Nexys4 to uderstand which kind of modification you needed? | 13:57 |
| andrzejr | bandvig, nope, just checked some of the existing configs. AFAIR this one: https://sourceforge.net/p/openocd/mailman/message/32110155/ | 14:01 |
| andrzejr | the only difference is vid/pid | 14:02 |
| olofk | Problem is that it looks like they (Digilent) use different chips on all boards | 14:15 |
| olofk | On Atlys it's apparently a Cypress FX2. On my lx9 microboard it's some Atmel MCU | 14:16 |
| olofk | If it's just an ordinary FTDI chip, andrzejr's method would most likely work fine | 14:16 |
| olofk | bandvig: And I'm not sure it matter if you get a Platform cable. You would still need OpenOCD to understand the protocol. Not sure it does that | 14:17 |
| olofk | ok, this is scary. The moment I started writing Cypress here, an ad for Cypress PSoC4 turned up in my browser :) | 14:18 |
| bandvig | :) | 14:25 |
| bandvig | olofk: I'm not sure about OpenOCD, but "Advanced JTAG Bridge" (from Advance Debug System package) should support "Xilinx Platform Cable USB" | 14:32 |
| bandvig | olofk: so I think the OpenOCD also should support it or it could be appropriatelly putched | 14:34 |
| bandvig | "patched" | 14:34 |
| olofk | bandvig: Oh, I didn't know that. In that case OpenOCD might support it already too | 14:42 |
| wallento | I think all digilent board use the same FTDI chip and firmware | 14:43 |
| wallento | oh, if any of you needs a jtag<->pmod adapter, I can provide some | 14:44 |
| wallento | very simple breakout board | 14:45 |
| wallento | I designed it for the ARM compatible JTAG adapters, such as the Olimex one | 14:45 |
| olofk | Only JTAG adapter I got is an old Actel FlashPro, and there aren't any drivers for that | 14:46 |
| olofk | I really should get one | 14:46 |
| olofk | Like the Olimex for example | 14:47 |
| olofk | wallento: I had to check the schematics for myself to be sure, but just as mithro says, it's not an FTDI chip on the Atlys, but a Cypress chip | 14:51 |
| olofk | So Digilent uses different USB-JTAG solutions for different boards | 14:51 |
| wallento | oh, crazy | 14:52 |
| wallento | I think they stopped this | 14:52 |
| wallento | and use their board module | 14:52 |
| wallento | that xilinx also uses | 14:53 |
| wallento | on large boards | 14:53 |
| wallento | on the most recent ones they only use their stuff | 14:53 |
| wallento | as they are somehow with fossi we may bring this topic up now :) | 14:53 |
| wallento | but the cypress is a nice chip | 14:53 |
| olofk | board module? | 14:53 |
| wallento | http://store.digilentinc.com/all-products/jtag-programmers/ | 14:53 |
| wallento | those SMT modules | 14:54 |
| olofk | Yes, I guess it's time for my yearly angry tweet to Digilent about their proprietary JTAG protocol :) | 14:54 |
| wallento | you can find them on xilinx boards, such as the kc705 | 14:54 |
| olofk | ah ok | 14:54 |
| wallento | they are identical to the subsystem on nexys and arty | 14:55 |
| olofk | The other option is to get a HS3 (or a platform cable, but they're much more expensive) and hook up to the 2x7 connector. That one has been pretty standard for many years now on Xilinx boards | 14:55 |
| wallento | by the way: I have also spoken to Trenz Electronics (http://www.trenz-electronic.de/) | 14:56 |
| wallento | they have really nice boards | 14:56 |
| olofk | ah. Nice. I've looked at their stuff many times before | 14:56 |
| olofk | Yes, indeed | 14:56 |
| wallento | they are part of the Librecores jury | 14:56 |
| wallento | nice folks to talk to | 14:56 |
| wallento | They will also be in Bologna and bring boards with them :) | 14:57 |
| olofk | Great! | 14:57 |
| -!- Netsplit *.net <-> *.split quits: fotis2 | 15:33 | |
| olofk | FuseSoC icestorm backend is more or less done now. Hope to push it soon | 17:40 |
| -!- Netsplit *.net <-> *.split quits: sandeepkr_ | 17:41 | |
| -!- Netsplit *.net <-> *.split quits: aburgess_ | 17:41 | |
| -!- Netsplit *.net <-> *.split quits: andrzejr | 17:41 | |
| -!- andrzejr_ is now known as andrzejr | 17:41 | |
| --- Log closed Mon Apr 18 00:00:26 2016 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!