| --- Log opened Sat Apr 16 00:00:23 2016 | ||
| wallento | jumbo, I would suggest the Nexys4 DDR board: https://reference.digilentinc.com/nexys4-ddr:start | 03:26 |
|---|---|---|
| wallento | there is academic pricing if you are or know a student | 03:26 |
| shorne | olofk: stekern: Before when we were talking dma controllers we mentioned wb_streamer, and another prehistoric dma controller | 05:11 |
| shorne | is that wb_dma? | 05:11 |
| mithro | So, does the mor1k have JTAG debugging using openocd on the Spartan 6? | 05:17 |
| shorne | mithro: I have been able to single step in gdb if that is what you mean | 05:22 |
| shorne | but on a xilinx board | 05:22 |
| shorne | over openocd | 05:23 |
| olofk | shorne: I think what stekern meant was that there are built-in DMA controllers in both the standard ethernet and VGA controller we usually use | 05:24 |
| olofk | wb_streamer is a standalone component | 05:25 |
| olofk | mithro: Yes, that should work, but you need to hook up JTAG to an external connector, not over the USB connector | 05:26 |
| olofk | Which really sucks. I can't understand why Digilent can't just open up their stupid JTAG over USB protocol. The Altera equivalent is reverse engineered, so for boards like de0_nano, we can just use the regular USB connector with OpenOCD | 05:27 |
| olofk | It's not very straightforward to use the Xilinx IP-XACT files in FuseSoC yet :/ | 05:29 |
| olofk | They define the same files in several filesets, and there isn't really a reliable way to filter that out automatically | 05:30 |
| olofk | But I have actually already thought about this and the plan has been to somehow disable filesets from the .core file for cases like this | 05:31 |
| mithro | olofk: I have open firmware for the Atlys board | 05:46 |
| mithro | sorry, I'm back now - My dinner turned up | 06:19 |
| mithro | shorne: How did you do that? | 06:19 |
| mithro | olofk: Can you point me to the code around the JTAG stuff? | 06:20 |
| olofk | mithro: Open firmware? For the onboard MCU? | 06:29 |
| mithro | olofk: yes, it emulates a Altera USB Blaster device | 06:29 |
| mithro | olofk: works well with openocd | 06:29 |
| olofk | Cool :) | 06:32 |
| mithro | olofk: I was sure I had mentioned that before? https://github.com/mithro/ixo-usb-jtag | 06:32 |
| olofk | I guess the next step then would be to instantiate a Xilinx bscan device then and connect that to adv_debug_sys | 06:32 |
| olofk | I wasn't aware. Do you know if that works for other boards too? I have an lx9 microboard with the same issue | 06:33 |
| mithro | olofk: The lx9 microboard was done by the makestuff guy? | 06:33 |
| mithro | I even have udev rules which will make the Atlys appear in the right way on plug in | 06:34 |
| mithro | And we even have debs at https://launchpad.net/~timvideos/+archive/ubuntu/fpga-support :P | 06:34 |
| olofk | So to sum it up. The current code for the Atlys OpenRISC SoC in FuseSoC uses PMOD->(opencores jtag tap)->adv_debug_sys | 06:34 |
| olofk | lx9_microboard is another Digilent board | 06:34 |
| olofk | haha. Nice. If I only had more time, I'd love to look that up in more detail :/ | 06:34 |
| mithro | olofk: does it have a Cypress FX2 on it? | 06:35 |
| olofk | With your firmware it would be MCU->(Xilinx BSCAN)->adv_debug_sys | 06:35 |
| shorne | olofk: I see, i am looking at wb_dma on opencores, I looked through wb_streamer too | 06:36 |
| mithro | olofk: Yeah | 06:36 |
| olofk | mithro: Haven't checked. Didn't know there was an FX2 on the Atlys actually. Thought it was some general ARM MCU | 06:36 |
| mithro | olofk: It looks like it has an Atmel | 06:36 |
| shorne | by half? | 06:36 |
| olofk | shorne: wb_dma is pretty old. I looked at it when I did wb_streamer, but I didn't think it was worth extending. | 06:37 |
| shorne | so.. I see wb_stream has both read and write, what do you mean by half dma/ | 06:37 |
| olofk | shorne: wb_dma has two wb master ports, so it can read a portion of the memory space and copy to another part | 06:37 |
| mithro | olofk: so adv_debug_sys is the tool running on the computer or the part? | 06:37 |
| shorne | I see, but wb_stream just has one port | 06:38 |
| olofk | mithro: It's the RTL code for the debug interface that we connect to OPenRISC | 06:38 |
| shorne | to do dma from one wb-client to another wb-client you need two | 06:38 |
| olofk | shorne: Yes, exactly, one read and one write | 06:38 |
| mithro | olofk: does it interface to the mor1k? or only the older implementation? | 06:39 |
| shorne | ok, that makese sense | 06:39 |
| olofk | shorne: So it would be memory -> wb_stream_reader -> wb_stream_writer -> memory | 06:39 |
| olofk | mithro: It works with or1200, mor1kx and the Pulpino guys use it for their RISC-V as well | 06:39 |
| shorne | olofk: and the stream protocol would just be a small intermediary step, nothing needs to be there really | 06:40 |
| olofk | shorne: In theory you should just be able to connect the stream ports to each other, but I'm not sure I have actually tried it. Should do a small testbench to try that | 06:40 |
| shorne | yeah, Ill try to wire them up and simulate in a small test | 06:41 |
| olofk | The drawback would be that you need to set up both the read and write parts to do a transfer, but I structured the RTL, so it should be possible to create a wrapper that sets up both at the same time | 06:41 |
| olofk | shorne: I have a simple bare-metal driver for the streamer too if you are interested | 06:42 |
| olofk | mithro: There is a host client part for adv_debug_sys as well, but we use OpenOCD instead | 06:43 |
| mithro | olofk: okay | 06:43 |
| olofk | There is another cool feature in adv_debug_sys too, so that you can tunnel a UART over JTAG | 06:43 |
| mithro | Is the opencores.org the current version at http://opencores.org/project,adv_debug_sys the current? | 06:44 |
| olofk | It works with OpenOCD as well, but there is some issue with the IRQ, so when Linux switches from polling to IRQ mode it stops working | 06:44 |
| olofk | mithro: I've done some fixes to my copy at github | 06:44 |
| olofk | olofk/adv_debug_sys | 06:44 |
| mithro | olofk: okay, so should use that? | 06:44 |
| olofk | Yes. | 06:45 |
| olofk | I'm hoping to get the stuff from pulpino merged in here as well in the future | 06:45 |
| olofk | Since OpenCores refuses to move from password protected svn repos and it's difficult to fix other people's cores I had to fork it :/ | 06:45 |
| olofk | mithro: If you want to try it in simulation, you can use the mor1kx-generic system in FuseSoC | 06:46 |
| olofk | If you run with --enable-jtag-vpi, the RTL will set up a socket connection which you can connect to from OpenOCD | 06:47 |
| olofk | There's a driver in mainline OpenOCD for that | 06:48 |
| mithro | olofk: okay | 06:56 |
| mithro | Its going to take a while to figure out how I can integrate this into MiSoC | 06:56 |
| mithro | What the JSP? | 06:57 |
| olofk | mithro: Hmm.. | 06:58 |
| olofk | Ahh.. that could be JTAG Serial Port | 06:58 |
| olofk | mithro: For MiSoC you already use mor1kx as a blackbox, right? Maybe you could just add an option to also instantiate an adv_debug_sys instance together with that | 07:00 |
| mithro | olofk: that was my thought :) | 07:00 |
| olofk | :) | 07:00 |
| olofk | That gives you the freedom to select jtag_tap, bscan, altera_virtual_jtag or jtag_vpi as your JTAG connector | 07:02 |
| olofk | I guess you could even do a UART-> JTAG adapter, so you can send JTAG commands over a UART. That would be cool | 07:03 |
| mithro | olofk: well, the jtag connector bit should probably happen at the higher level as misoc supports a wide range of boards | 07:03 |
| olofk | mithro: Yes, exactly, that would be a target-specific thing | 07:03 |
| shorne | olofk: I might be, I was reading through the linux driver, but at first I would just git up the verilog test bench and check in vsim | 07:05 |
| mithro | I had our bios booting on the or1k but I've broken it somehow | 07:05 |
| shorne | btw, last time I tried running vsim on fedora it was not working. Does anyone know the state now? | 07:08 |
| shorne | not working meaning, some libs were not longer available, cant remember exacts | 07:08 |
| shorne | fedora 23 | 07:08 |
| olofk | shorne: You can use icarus | 07:08 |
| olofk | I just noticed that I haven't pushed wb_streamer to the FuseSoC core library. Weird | 07:09 |
| shorne | olofk: I was reading from your repo | 07:10 |
| shorne | that was no problem finding it | 07:10 |
| shorne | Thanks ill try icarus, I have just been using the quartus bundled tools now, better try the free ones | 07:11 |
| olofk | shorne: Are you using FuseSoC? | 07:12 |
| shorne | yes | 07:14 |
| olofk | Then you can just add the path to your downloaded wb_streamer repo (or add --cores-root=/path/to/wb_streamer to the command line) and run fusesoc sim wb_streamer | 07:15 |
| olofk | or fusesoc sim wb_streamer --vcd to get a VCD file | 07:15 |
| olofk | fusesoc sim wb_streamer sim --help to get all supported options | 07:16 |
| olofk | no | 07:16 |
| olofk | fusesoc sim wb_streamer --help | 07:16 |
| mithro | olofk: where can I find the adv_debug_sys wired to the cpu? | 07:26 |
| olofk | https://github.com/openrisc/orpsoc-cores/blob/master/systems/mor1kx-generic/rtl/verilog/orpsoc_top.v | 07:27 |
| olofk | I think we have a system as well that uses JSP, but I'm not sure where that is | 07:28 |
| shorne | olofk: cool, I just knew fusesoc build up until now. Is there a command to generate the wb_intercon too? or need to run the script manually? | 08:19 |
| shorne | I used fusesoc pgm too :) | 08:21 |
| mithro | olofk: do you have any examples of using the xilinx jtag adapter thingy? | 08:27 |
| mithro | olofk: It's kind of interesting that my code emulates an Altera USB Blaster which means it might work with the non-openocd stuff in adv_dbg_if | 08:29 |
| mithro | oh it looks like that doesn't support the spartan 6 anyway... | 08:30 |
| olofk | shorne: There is no mechanism for regenerating wb_intercon automatically yet. It's been on my todo list for a few years, but now we're getting close actually :) | 08:37 |
| olofk | mithro: Don't think I have any examples unfortunately | 08:37 |
| olofk | mithro: Ah.. you still need support for xilinx bscan in OpenOCD? | 08:38 |
| mithro | olofk: hrm? | 08:39 |
| olofk | Or did I misunderstand? | 08:39 |
| mithro | olofk: The code at https://github.com/olofk/adv_debug_sys/blob/master/Hardware/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v doesn't support the Spartan 6 BSCAN module... | 08:58 |
| mithro | so, this seems to be kind of maybe compiling | 08:59 |
| mithro | olofk: once this has compiled, I should see the debug interface in a jtag scan? | 08:59 |
| olofk | mithro: JTAG is mostly magic to me, so I'm not sure | 09:18 |
| mithro | okay :) | 09:18 |
| olofk | But yes, you would need to find an instance that works for Spartan6, and then hopefully you should see at least the JTAG tap | 09:18 |
| mithro | olofk: so, what would you "do" on the openocd side? | 09:19 |
| olofk | But I'm not sure if you need separate OpenOCD drivers for the different JTAG taps, or if they are just protocl ocnverters | 09:19 |
| olofk | mithro: I run this for the de0_nano -> openocd -f interface/altera-usb-blaster.cfg -f board/or1k_generic.cfg | 09:20 |
| mithro | olofk: okay great! | 09:20 |
| olofk | But maybe you need to change the JTAG id somewhere. _franck_ is your friend here :) | 09:20 |
| olofk | It's really cool if this works | 09:21 |
| olofk | But the best thing would of course be if Digilent just opened up their protocol so we can use the same procedure for the other Digilent boards too | 09:21 |
| mithro | well, now I need to figure out wtf a FPGATAPID is :P | 09:23 |
| mithro | It seems like I didn't break the core, my firmware still boots.... | 09:32 |
| mithro | well... | 09:33 |
| mithro | https://www.irccloud.com/pastebin/Dxy1sTQC/ | 09:34 |
| mithro | olofk: I think it kind of found the tap..... | 09:35 |
| mithro | Looks like someone might have added SPARTAN6 support... https://github.com/aurabindo/aura-soc/blob/e7cfed424170f1c183cc25d4aa95db25a1eb60e3/rtl/verilog/adv_debug_sys/Hardware/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v | 09:42 |
| mithro | Heard of aura-soc at all? | 09:42 |
| mithro | hrm... the fact that he is driving both TMS and TDO with debug_tdo_i makes me think this might not work... | 09:43 |
| mithro | ooo... | 09:48 |
| mithro | https://github.com/xfguo/adv_debug_sys/commits/db55d1166e04428327c115c819fa8fc32ca5bcf8/Hardware/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v | 09:48 |
| mithro | Lets test random code on the interwebs :P | 10:08 |
| mithro | I'm pretty sure those comments are wrong.... | 10:09 |
| mithro | so I think I've set the FPGATAPID correctly now | 10:33 |
| mithro | but it is very unclear to me if openocd is correctly talking to the core or not | 10:33 |
| mithro | oh - it might be! | 10:35 |
| mithro | Chip is or1200.cpu, Endian: big, type: or1k | 10:35 |
| mithro | Now to fix the reset... | 10:35 |
| mithro | olofk: so, once I have openocd kind of working, how do I actually connect gdb to it or something? | 10:36 |
| mithro | Want to inspect the registers and stuff... | 10:37 |
| mithro | oh, when is _franck_ generally around? | 10:40 |
| mithro | Getting closer I think... | 10:44 |
| mithro | https://www.irccloud.com/pastebin/HtWOPhG3/ | 10:44 |
| wallento | mithro: you can have a look at the de0 nano tutorial | 11:27 |
| wallento | once you have "Chip is or1200.cpu, Endian: big, type: or1k", the rest is the same | 11:28 |
| olofk | mithro: This is great! | 11:35 |
| mithro | I broke it again.... | 11:35 |
| olofk | But it makes me so sad to see that you find all these random forks with one fix each on the internet. This is one of the main things I wanted to fix with FuseSoC | 11:35 |
| mithro | olofk: yeah, I frequently find people's patches and send them upstream for them | 11:37 |
| mithro | I'm not sure how to debug the burst read stuff | 11:38 |
| mithro | The error sounds like it is failing to read stuff from the wishbone bus? | 11:42 |
| mithro | Which I assume is when the adbg_top is acting as a master on the wishbone bus? | 11:43 |
| olofk | mithro: Yes, that's correct | 11:43 |
| mithro | Why is it trying to read 0x400 ? | 11:43 |
| olofk | adv_debug_sys has several interfaces. One is used to control the CPU directly, for things like stopping and starting the CPU and read internal regs. The other is a wishbone master that you connect to you regular memory bus | 11:44 |
| olofk | 0x400 is one of the exception vectors, right? | 11:44 |
| olofk | Can't remember which one | 11:44 |
| olofk | Instruction page fault according to the spec | 11:44 |
| olofk | No matching PTE found in page tables or page | 11:44 |
| olofk | protection violation for instruction fetch. | 11:44 |
| olofk | Fuck knows what that means. Probably something with computers | 11:45 |
| olofk | So are you doing anything to get this error, or does it happen when you connect? | 11:45 |
| olofk | And what SoC are you using? Is it a modified version of the FuseSoC system, or a MiSoC-based one? | 11:46 |
| olofk | I agree that it feels like you're close, so it would be cool to get this working | 11:47 |
| mithro | MiSoC based one | 11:47 |
| olofk | mithro: Is this the current situation in OpenOCD? https://www.irccloud.com/pastebin/Dxy1sTQC/ | 11:49 |
| mithro | olofk: no, gotten further than that | 11:49 |
| mithro | https://www.irccloud.com/pastebin/udAPodW4/ | 11:51 |
| mithro | That is what happens if my CPU is already halted when I call openocd | 11:52 |
| mithro | However, if I try and use openocd while the CPU is running, it fails when it tries to "save the context" | 11:53 |
| olofk | mithro: Could the CPU be reset? That's a classic :) | 11:54 |
| olofk | IIRC you need to separate the system reset and the debug reset | 11:54 |
| mithro | olofk: what do you mean? | 11:54 |
| olofk | Check here for details https://github.com/openrisc/orpsoc-cores/blob/master/systems/de0_nano/rtl/verilog/orpsoc_top.v | 11:54 |
| mithro | You guys do | 11:55 |
| mithro | assign or1k_rst = wb_rst | or1k_dbg_rst; | 11:55 |
| olofk | yep | 11:55 |
| mithro | olofk: which I also do | 11:55 |
| olofk | Where wb_rst is a power-on reset more or less and or1k_dbg_reset is controlled from adv_debug_sys | 11:55 |
| olofk | ah ok | 11:55 |
| olofk | Then it's not that | 11:55 |
| mithro | olofk: we have a different RESET_PC than you? | 11:56 |
| mithro | so, it seems to be failing in the "int shift = find_status_bit(in_buffer, STATUS_BYTES);" when doing the read | 11:58 |
| olofk | Just a thought. Maybe you need to enable some options in mor1kx. stekern is the expert here | 11:59 |
| mithro | Does "ocd_or1200.cpu ocd_or1200.cpu cget -endian" actually cause anything to be read out of jtag? | 12:00 |
| mithro | oh | 12:00 |
| mithro | .FEATURE_DEBUGUNIT("ENABLED"), | 12:00 |
| mithro | What is | 12:02 |
| mithro | .OPTION_RF_NUM_SHADOW_GPR(1), | 12:02 |
| mithro | ? | 12:02 |
| wallento | mithro: richard herveille wrote the most recent adv_dbg_sys variant, he fixed it and improved the code a bit | 12:05 |
| wallento | https://github.com/RoaLogic/adv_dbg_if | 12:05 |
| wallento | You are right, this needs to be fixed up. | 12:05 |
| wallento | I will release a preview of opensocdebug the next weeks | 12:06 |
| wallento | for the arty and nexys board | 12:06 |
| wallento | there the debug transport is UART, which is much faster | 12:06 |
| wallento | turnaround is better | 12:06 |
| mithro | TODO: Real hardware tests | 12:06 |
| wallento | its in silicon | 12:07 |
| wallento | I think this is what this means | 12:07 |
| mithro | wallento: so, should I be using that code rather than the one olofk pointed me too? | 12:08 |
| mithro | IOOOOOOOOOOOOOOOOOOOOOO! | 12:11 |
| mithro | https://www.irccloud.com/pastebin/lpHVPZVl/ | 12:12 |
| mithro | It might be working!~@? | 12:12 |
| wallento | mithro: I would give it a shot | 12:12 |
| wallento | but seems you don't need to :) | 12:12 |
| mithro | Turns out you should enable the debug unit before trying to use it I think :P | 12:13 |
| mithro | wallento: ../or1k-dev.tcl doesn't appear to exist anywhere.... | 12:14 |
| wallento | https://github.com/openrisc/tutorials/blob/master/or1k-dev.tcl | 12:14 |
| mithro | Well, I appear not to have or1k-elf-gdb | 12:19 |
| wallento | https://github.com/openrisc/newlib/releases/tag/v2.3.0-1 | 12:20 |
| wallento | this is statically linked, so it should run everywhere | 12:21 |
| mithro | wallento: you guys seem to have binutils and gdb in the same repository? | 12:25 |
| wallento | yes, thats the same upstream | 12:25 |
| wallento | its the standard binutils-gdb repo | 12:25 |
| wallento | https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git | 12:26 |
| wallento | I think they are in the same because they share the bfd and opcodes stuff | 12:26 |
| mithro | wallento: interesting, the tarballs they produce look very different... | 12:27 |
| wallento | I think its filtered then | 12:27 |
| olofk | mithro: This is a historical thing where they used to have everything in the same repo. They have split out gcc (I think) since then | 12:27 |
| olofk | And currently upstream binutils-gdb repo lacks gdb for OpenRISC | 12:27 |
| wallento | https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob;f=src-release.sh;h=64fa4c2120bfb81a02d99bc4e73b8b10ea6e8592;hb=HEAD | 12:27 |
| olofk | But I don't really use that | 12:28 |
| olofk | You can do most stuff directly from OpenOCD | 12:28 |
| olofk | Like loading programs, reading and writing memories and registers | 12:28 |
| wallento | actually openocd supports more than gdb I think | 12:28 |
| olofk | My daughter demands computer time now. bbl :) | 12:28 |
| mithro | it seems to be working... | 12:32 |
| mithro | how do I step? I thought it would be stepi/nexti? | 12:32 |
| wallento | stepi is on assembly level | 12:33 |
| wallento | did you see this: https://github.com/openrisc/tutorials/blob/master/docs/Debugging.md | 12:33 |
| mithro | nope! | 12:34 |
| mithro | \o/ | 12:37 |
| mithro | https://www.irccloud.com/pastebin/OgsBQDZ1/ | 12:37 |
| wallento | olofk: https://cloud.githubusercontent.com/assets/299017/14582486/976b9a7a-0406-11e6-954e-9fbc0695f09c.png | 13:08 |
| wallento | mithro: nice! | 13:08 |
| olofk | mithro: Great! | 13:09 |
| olofk | wallento: Cool!! | 13:09 |
| wallento | I don't like the layout it generates, but I assume this is something the user should do with graphviz then | 13:09 |
| wallento | this is just dot -Tpng <in> > <out> | 13:09 |
| _franck_ | mithro: I guess you don't need me anymore :) | 15:51 |
| _franck_ | FYI, I think andrzejr did use OpenOCD with a Digilent board and it's original firmware/interface | 15:52 |
| andrzejr | _franck_, mithro, yes, it worked just fine. | 15:56 |
| andrzejr | used that openocd script: https://github.com/andrzej-r/orpsoc-cores/blob/nexys4ddr/systems/nexys4ddr/nexys4ddr_top/sw/nexys4ddr.tcl | 15:56 |
| andrzejr | and this top level rtl: https://github.com/andrzej-r/orpsoc-cores/blob/nexys4ddr/systems/nexys4ddr/nexys4ddr_top/rtl/verilog/orpsoc_top.v | 15:58 |
| olofk | andrzejr: What do you think, should we add an extra_files option to the logicore provider? | 16:16 |
| andrzejr | olofk, I guess so. | 16:17 |
| andrzejr | I don't mind changes, my version was just a bare minimum to get it working. | 16:18 |
| olofk | andrzejr: I like minimum. It means less things that can go wrong :) | 16:21 |
| olofk | andrzejr: logicore provider pushed. That only took about a year :) | 16:46 |
| olofk | andrzejr: I saw this patch also. I think you can drop it since FuseSoC supports setting library names now https://github.com/andrzej-r/orpsoc-cores/blob/nexys4ddr/cores/xilinx_mii_to_rmii/patches/0001-Switched-to-work-library.patch | 16:47 |
| olofk | You need to update the core file though | 16:48 |
| andrzejr | Have you got any examples? | 16:48 |
| olofk | https://github.com/openrisc/orpsoc-cores/blob/master/cores/libaxis/libaxis-1.0.core | 16:49 |
| olofk | It's logical_name | 16:49 |
| olofk | Weird name, I know, but that's what it's called in IP-XACT | 16:50 |
| andrzejr | I meant examples of cores generated with logicore :-) | 16:52 |
| olofk | oh | 16:53 |
| andrzejr | (but the libraries are useful too) | 16:53 |
| olofk | I have a few that we use at work, but nothing pushed | 16:53 |
| olofk | So your mii_to_rmii core might be the first one | 16:53 |
| andrzejr | does it only need extra_files ? | 16:54 |
| olofk | Which one? | 16:54 |
| andrzejr | mii_to_rmii. But this one doesn't need any extra files. What did you mean by "you need to update the core file"? | 16:57 |
| olofk | andrzejr: Oh, I mean for the logical_name stuff | 17:03 |
| olofk | To drop the patch | 17:03 |
| olofk | andrzejr: I'll just do the same change to the coregen provider and push it now | 17:06 |
| andrzejr | OK, thanks. I need to go through by bit-rotted code and update it to the new version of orpsoc-cores and fusesoc. | 17:09 |
| olofk | Thanks for the patches, and for your patience. Sorry that it's taken so long | 17:09 |
| andrzejr | wallento, I've seen your nexys4 repo. I see you chose to generate ddr i/f with vivado (that's is good decision, given how much headache coregen version gave me) | 17:12 |
| wallento | yes, I still use yours as reference | 17:13 |
| andrzejr | but how are you going to use axi4 interface | 17:13 |
| wallento | there is an wb2axi I started | 17:13 |
| wallento | actually I am wiring it up at this minute :) | 17:13 |
| wallento | I tried to split it up | 17:13 |
| andrzejr | oh, that's cool. | 17:13 |
| wallento | there is a "board core", like nexys, arty, de0nano | 17:14 |
| wallento | they encapsulate all IP | 17:14 |
| wallento | then there is mor1kx_soc, my various optimsoc toplevels, pulpino, name it | 17:14 |
| andrzejr | my wb2ui was another source of problems :-) I hope you managed it better. | 17:14 |
| wallento | and both are then just wired by a toplevel | 17:14 |
| wallento | yeah, I made the same experience | 17:14 |
| wallento | I had a student that spent multiple months on wb2mig for the XUPV5 board | 17:15 |
| wallento | is was a pain | 17:15 |
| wallento | timing was never met and we always had functional errors | 17:15 |
| wallento | with the AXI itnerface I can trust to an interface I really understand :) | 17:15 |
| wallento | and the wb2axi is dumb for the start | 17:16 |
| wallento | the biggest issue that you cannot handle bursts properly | 17:16 |
| wallento | because linear bursts are undetermined in length | 17:16 |
| andrzejr | yeah, I wish mor1kx supported axi natively. | 17:16 |
| wallento | I started it a while ago | 17:17 |
| wallento | because I wrote an AXI interface for the Cortex-M0/M1 when I worked at ARM | 17:17 |
| wallento | and I worked on the mor1kx storage path | 17:17 |
| wallento | but somehow I never focused on this part | 17:17 |
| andrzejr | My wb2axi almost worked, I fixed some errors that were only visible in HW (that's why diila is instantiated). But even then I was hitting some issues with bursts enabled. | 17:18 |
| wallento | ah, okay, where is it? | 17:18 |
| andrzejr | sorry, wb2ui | 17:18 |
| wallento | okay | 17:19 |
| wallento | yeah, this is painful | 17:19 |
| wallento | I already spent like half an hour udnerstanding the clocking from the spec :) | 17:19 |
| wallento | I currently try to simulate the whole design | 17:19 |
| andrzejr | what simulator do you use? | 17:20 |
| wallento | but I am not sure if I can trigger the DDR model from tcl | 17:20 |
| wallento | because of copyright stuff | 17:20 |
| wallento | xsim or isim or whatever this thing in vivado is called :) | 17:20 |
| wallento | so, for the first I am just running stuff from the user interface | 17:20 |
| wallento | but have no clue if I can do it as a sideproduct | 17:21 |
| andrzejr | try the new logicore (vivado) provider olofk just pushed. With coregen (ise) I had to add some extra files, though. | 17:23 |
| olofk | The pulp guys put AXI buses on their OpenRISC core (or10n) from the beginning | 17:23 |
| wallento | I think I will do this sometime in 2016 | 17:24 |
| olofk | I really really really hate Xilinx's UI bus. It is underdocumented and contains subtle changes between the FPGA families and ISE/Vivado releases | 17:24 |
| andrzejr | afair lowrisc is generating ddr i/f using vivado. | 17:24 |
| wallento | yes, it is adopted from there actually ;) | 17:25 |
| wallento | but they use another ddr model | 17:25 |
| wallento | for verilator sim | 17:25 |
| wallento | I would prefer jsut to generate it | 17:25 |
| wallento | but if I run synthesis it does not generate the model | 17:25 |
| olofk | andrzejr: I tried to regenerate your nexys4ddr_ddr2 core with the pushed coregen provider. It works even though I don't add the .prj and .cgc file. Do you know if this means that they are not needed, or if the generated core turns out bad? | 17:27 |
| wallento | I think the prj is always necessary | 17:28 |
| wallento | it contains the pins, right? | 17:28 |
| olofk | That is what I remember too | 17:28 |
| andrzejr | afair there were some difference (ddr3 vs ddr2 if I remember correctly) | 17:29 |
| olofk | Yep, I just diffed with and without the prj file. It just randomly assigns pins without it | 17:29 |
| andrzejr | without extra files some settings were lost | 17:29 |
| olofk | And gets the clock wrong | 17:29 |
| olofk | Alright. Then we know that extra_files work at least :) | 17:29 |
| olofk | andrzejr: Trying to rebuild the whole nexys4ddr_top now | 17:31 |
| andrzejr | naah.. I would be surprised if that still worked. | 17:32 |
| wallento | so, guys, I am off to bed now, I will commit some stuff the next week I think for the nexys board module and wb2axi | 17:32 |
| andrzejr | wallento, thanks. I'm eager to try your code | 17:33 |
| olofk | wallento: Cool | 17:33 |
| olofk | andrzejr: I'm having problems regenerating the mii_to_rmii core | 17:36 |
| olofk | ahh.. I think it's because of the stupid idea of putting the Vivado version in the xci file | 17:37 |
| olofk | ok, solved half of the problem :) | 17:46 |
| olofk | andrzejr: First problem can be solved by adding upgrade_ip [get_ips xilinx_mii_to_rmii] | 17:48 |
| olofk | after read_ip | 17:48 |
| olofk | But unfortunately this upgrades the ip from v2.0 to v2.0.8, so all paths change | 17:49 |
| olofk | Actually... I think we can get around this by getting the files from the IP-XACT file instead | 17:49 |
| olofk | But that doesn't work yet in FuseSoC. Need to patch a few things, but I got most of it working yesterday so it's not too much of an issue | 17:50 |
| olofk | oh... my ipxact parser doesn't fetch logicalName from the XML file | 18:02 |
| olofk | I give up. Close, but not there yet | 18:16 |
| olofk | But I think it will be nice once it's done | 18:16 |
| olofk | Then we won't have to list the files as long as coregen/vivado generates an IP-XACT file that we can use to parse the file list | 18:17 |
| mithro | olofk: https://github.com/olofk/adv_debug_sys/pull/1 | 22:00 |
| --- Log closed Sun Apr 17 00:00:25 2016 | ||
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