| --- Log opened Sat Dec 02 00:00:30 2017 | ||
| --- Day changed Sat Dec 02 2017 | ||
| bandvig | shorne: Which memory consistency model(s) is(are) implemented in hardware/software for your OpenRISC SMP machine? | 12:39 |
|---|---|---|
| bandvig | Please, do not hesitate to answer even if I disconnected. I read Julius log periodically. | 12:54 |
| shorne | bandvig: I hope it answers, but there are 2 things built into mor1kx | 20:50 |
| shorne | 1. the lwa/swa instructions imply a pipeline flush and sync to memory | 20:51 |
| shorne | 2. the caches have a snoop interface to watch any wishbone writes and clear(refresh) cachelines | 20:51 |
| shorne | its in the spec, are you asking about something else? | 20:52 |
| --- Log closed Sun Dec 03 00:00:42 2017 | ||
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