| --- Log opened Wed Sep 20 00:00:53 2017 | ||
| shorne | ZipCPU|Laptop: on hacker news front page again. hope thats a good thing :) | 00:19 |
|---|---|---|
| stekern | this one, right? http://zipcpu.com/blog/2017/09/18/clocks-for-sw-engineers.html | 02:32 |
| stekern | ZipCPU|Laptop: good writeup | 02:32 |
| stekern | I would like to see the inverse of it written for hw engineers diving into sw development as well ;) | 02:33 |
| ZipCPU | shorne: stekern: Thank you | 07:05 |
| ZipCPU | stekern: A writeup for hardware engineers diving into S/W development might be useful. | 07:05 |
| ZipCPU | At this point in time, though, I don't think I could write it. I'm just not familiar enough (yet) with how h/w engineers (not just digital logic designers) think | 07:06 |
| mtn2 | Hi, Anyone implemented mor1kx in Digilent Nexys3/4 FPGA and booted linux? | 09:17 |
| gdevic | Hi, I am the author of A-Z80 CPU at OpenCores (https://opencores.org/project,a-z80) read on freecores to try to contact you here on getting some help importing that core to the freecores. Can you help me, or refer to someone who could? Thanks! | 16:32 |
| shorne | mtn2: I havent run on any digilent boards, how different is nexys3/4 from the ones we support? | 18:06 |
| shorne | https://github.com/openrisc/orpsoc-cores/tree/master/systems | 18:06 |
| shorne | Myabe its the DDR controller, I think our current boards all use a single rate sdram-controller | 18:07 |
| shorne | gdevic, if you check the openrisc web history I hope you see this, mithro should be able to help you getting your code on freecores | 18:09 |
| shorne | There is also https://www.librecores.org now | 18:09 |
| mafm | shorne: gdevic left | 18:16 |
| --- Log closed Thu Sep 21 00:00:54 2017 | ||
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