| --- Log opened Thu Mar 02 00:00:24 2017 | ||
| mithro | wallento: Any chance you'll get to look at my email about OpenDebugSoC? | 01:33 |
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| -!- karan__ is now known as karan | 12:49 | |
| shorne | wallento: stekern_: I have been looking at the SMP code in the kernel and usage of shadow regs. Is this different from shadow regs in the SPEC? | 23:09 |
| shorne | i.e. in the spec there is a way to check CPUCFGR for count of shadow regs. But we dont do that in the kernel | 23:09 |
| shorne | also there is a SR[CID] we can enable to do context incrementing, but it seem we dont do that | 23:09 |
| shorne | or is the implementation all according to spec? | 23:12 |
| stekern_ | shorne: the implementation should be spec-compliant | 23:13 |
| stekern_ | but I can't remember all the gory details off teh top of my head | 23:13 |
| stekern_ | we only use the shadow regs as scratch regs though | 23:14 |
| -!- stekern_ is now known as stekern | 23:14 | |
| stekern | we're not using them *as* the actual registers ever | 23:15 |
| stekern | the history in a nutshell is, we needed scratch reg to save state (since the hack with using the mem area around 0x0 doesn't work for smp), and I found that we could use the shadow regs without needing to do any spec changes | 23:17 |
| shorne | stekern: ah, thanks that makes sense then as to why we are not using the "fast switching" stuff. i.e. we never set SR[CE] | 23:26 |
| shorne | we are not using shadows for exception nesting, just for scratch | 23:26 |
| shorne | thanks, clear now | 23:27 |
| shorne | stekern: actually one question, do you think it would make sense to remove the CONFIG_OPENRISC_HAVE_SHADOW_GPRS and replace with a check to CPUCFGR? | 23:32 |
| shorne | We dont really want to do that at runtime for every save/load would need something tricky, like alternatives | 23:34 |
| stekern | yeah, I think that's why I went with the config option | 23:34 |
| --- Log closed Fri Mar 03 00:00:25 2017 | ||
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