| --- Log opened Sun Oct 16 00:00:59 2016 | ||
| kc5tja | I doubt it. | 00:41 |
|---|---|---|
| kc5tja | WIP datasheet for KCP53000 CPU -- https://github.com/sam-falvo/polaris/blob/master/docs/SUMMARY.md . Let me know what you think! | 01:02 |
| promach | I am now figuring out how to synthesise openrisc mor1kx with yosys | 03:06 |
| promach | anyone have links for this ? | 03:06 |
| SMDhome | promach: http://www.clifford.at/icestorm/ could that help? | 06:52 |
| promach | SMDhome: not really | 07:00 |
| promach | unless I missed some link within it ? | 07:00 |
| promach | I even saw http://opencircuitdesign.com/qflow/ | 07:01 |
| SMDhome | kc5tja: .svg file is not shown inside text but available directly. Ialso thing it would be nice if you add some bus names to it. Everything else looks nice. | 07:01 |
| promach | but no exact tutorials on how to do it | 07:01 |
| SMDhome | I guess there are no exact tutorials on that. Do you want to build mor1kx using yosis and then upload it to lattice fpga or smth else? | 07:02 |
| promach | yeah | 07:04 |
| SMDhome | promach: Then I'd suggest to try that part of my link: | 07:05 |
| SMDhome | yosys -p "synth_ice40 -blif rot.blif" rot.v | 07:05 |
| SMDhome | arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.asc | 07:05 |
| SMDhome | icepack rot.asc rot.bin | 07:05 |
| SMDhome | iceprog rot.bin | 07:05 |
| SMDhome | synthesize - pnr - pack - flash | 07:05 |
| promach | part of your link ? | 07:05 |
| SMDhome | >http://www.clifford.at/icestorm/ | 07:06 |
| SMDhome | There is caption "How do I use the Fully Open Source iCE40 Flow?" | 07:06 |
| promach | I see | 07:07 |
| promach | this targets a single standalone verilog file | 07:07 |
| SMDhome | Ok, then we need to ask olofk how to get compilation line for mor1kx for icarus sim from fusesoc | 07:08 |
| SMDhome | promach: do you have fusesoc? | 07:10 |
| promach | that was installed on my old laptop | 07:10 |
| promach | I need to get it here on my new platform | 07:10 |
| promach | by the way, I am new to openRISCC | 07:11 |
| SMDhome | I suggest you to get it or at least take a look at git repo: ie there is smth like systems/de1/rtl/verilog/orpsoc_top.v which I guess is wrap(top file) for SoC for de1 | 07:12 |
| promach | give me 10 minutes | 07:12 |
| SMDhome | And I think you should use yosis like: firstly configure mor1kx core(choose pipeline and features you want) and then yosis orpsoc_top.v -I<list all directories than contain files> | 07:14 |
| SMDhome | promach: >by the way, I am new to openRISCC | 07:14 |
| SMDhome | Me neither :) | 07:14 |
| promach | wow, you are to humble | 07:15 |
| promach | too | 07:15 |
| promach | I am not using DE1 | 07:16 |
| promach | I do not have DE1 | 07:16 |
| SMDhome | that is only example | 07:17 |
| promach | https://github.com/openrisc/mor1kx/search?utf8=%E2%9C%93&q=orpsoc_top.v | 07:18 |
| SMDhome | promach: check here https://github.com/openrisc/orpsoc-cores/tree/master/systems | 07:18 |
| promach | how do I get the latest code for mor1kx with fusesoc ? | 07:19 |
| promach | let say I simulate and synthesise without any thought of any specific FPGA architecture | 07:20 |
| promach | how would I do it ? | 07:20 |
| SMDhome | promach: let's clarify, there is mor1kx core and there is SoC that uses mor1kx core and has interfaces to memory, jtag, etc | 07:22 |
| SMDhome | <That's the time olofk_ should trigger after naming fusesoc so many times :)> | 07:22 |
| SMDhome | You download and install fusesoc, then for simple simulation you could just run: fusesoc sim --sim=verilator/icarus mor1kx-generic --elf-load=bla.bin | 07:22 |
| SMDhome | mor1kx-generic serves only for simulation purposes | 07:23 |
| promach | SoC that uses mor1kx core ? | 07:24 |
| SMDhome | Are you familiar with SoC term or should I explain? | 07:24 |
| promach | System on chip | 07:24 |
| promach | you are saying that I need SoC besides the core ? | 07:25 |
| promach | I am really confused now | 07:25 |
| SMDhome | Yep, SoC could contain cpu core, mem controller, some periph connected to a bus, while mor1kx - is just a cpu core | 07:25 |
| promach | ok | 07:25 |
| SMDhome | So fusesoc makes SoC for you | 07:25 |
| promach | fusing all peripherals together with mor1kx ? | 07:26 |
| SMDhome | Yep | 07:26 |
| promach | ok | 07:26 |
| promach | let me try simulation | 07:26 |
| SMDhome | promach: do you have myStorm board or icoBoard? | 07:27 |
| promach | not yet now | 07:28 |
| promach | I have Parallella Desktop or some other Altera board | 07:28 |
| promach | now | 07:28 |
| promach | I have https://dpaste.de/f6Co error | 07:28 |
| SMDhome | Do you really have a binary at /home/phung/bla.bin? | 07:29 |
| SMDhome | And is it really elf for openrisc? | 07:30 |
| promach | I just ran | 07:32 |
| promach | fusesoc sim --sim=icarus mor1kx-generic --elf-load=bla.bin | 07:32 |
| promach | and did nothing else | 07:32 |
| SMDhome | --elf-load=bla.bin - you pass binary file to be executed on your simulation | 07:34 |
| SMDhome | Do you have a toolchain for openrisc? | 07:34 |
| promach | http://opencores.org/or1k/OpenRISC_GNU_tool_chain#Linux_.28uClibc.29_toolchain_.28or1k-linux-uclibc.29 | 07:36 |
| promach | I also need to get this as well | 07:36 |
| SMDhome | Sure. I could get you a binary that prints from 1 to 100 so you could test fusesoc | 07:37 |
| olofk_ | I heard you calling! | 07:40 |
| olofk_ | But actually, I just logged in to temporarily shut down this computer for a little while. Sorry about that. I'll be back in a while to show the insurmountable powers of FuseSoC | 07:42 |
| SMDhome | olofk_: since wallento is afk, do you know anything about optimsoc and how to use it for running multi-core setup for mor1kx? | 07:42 |
| olofk_ | I did try to build a basic OpenRISC-based SoC with icestorm a while ago too. Never completed it | 07:42 |
| SMDhome | or should I stick with http://www.optimsoc.org/docs/2016.1/user-guide.pdf | 07:43 |
| olofk_ | SMDhome: I don't know much about the internal details, but it seems like they have put some effort into documentation and build/simulation scripts | 07:43 |
| olofk_ | Sorry. gtg | 07:43 |
| promach | SMDhome: can I use https://aur.archlinux.org/packages/uclibc/ ? | 07:50 |
| SMDhome | promach: I have never tested that, I'm using newlib toolchain for baremetal :( | 07:53 |
| ZipCPU | promach: olofk will come back. He's a wonderful OpenRISC resource here, one of the few who tends to answer channel comments. | 08:11 |
| ZipCPU | What you may be missing is the flow: Yes, FuseSoC is used to aggregate various components together into a composite whole. | 08:11 |
| ZipCPU | FuseSoC aggregates existing known components, such as SMDhome explained: CPU, memory controller, UART, etc. | 08:12 |
| ZipCPU | FuseSoC, though, needs a system component to do so. | 08:13 |
| ZipCPU | The system component tells FuseSoC what components to get, how to aggregate them, etc. | 08:13 |
| ZipCPU | It's sort of the "toplevel" of a design. | 08:13 |
| promach | https://github.com/openrisc/tutorials#tutorials | 08:32 |
| olofk | Happy to be back. Thought for a while that my trusty rPi had given up for good | 08:47 |
| -!- knz_ is now known as knz | 10:36 | |
| kc5tja | SMDhome: That is a rendering bug on the part of the web browser. I have no control over that, I'm afraid. :( | 13:06 |
| kc5tja | (the lack of bus names and register names in the block diagram; if anyone has ANY idea how to fix this, please PLEASE let me know.) | 13:06 |
| kc5tja | For those wondering, you can synthesize a design with multiple Verilog components by simply listing all the components on the command-line. Throwing them all in a directory D and doing something like "yosys -p '...' D/*.v" is sufficient. | 13:08 |
| ZipCPU | kc5tja: I may not know the answer to your requested problem, but ... can you at least describe the problem? | 13:38 |
| ZipCPU | I'm looking for the reference of the block diagram with neither bus names nor register names in it. | 13:38 |
| ZipCPU | Can you tell me where I should look? What format the diagram is in? etc? | 13:38 |
| kc5tja | ZipCPU: The diagram is here: https://github.com/sam-falvo/polaris/blob/master/docs/block-diagram.svg | 17:20 |
| kc5tja | ZipCPU: But if you open the file in Inkscape, you'll notice that everything is labelled correctly. | 17:20 |
| ZipCPU | kc5tja: Try this: "inkscape -D -z --file=block-diagram.svg --export-eps=block-diagram.eps" | 20:46 |
| ZipCPU | That should maintain the quality of the svg image, while turning into a ... more usable format. ;) | 20:46 |
| kc5tja | I cannot view EPS on the web. | 20:47 |
| kc5tja | Not as an inline image. | 20:47 |
| ZipCPU | kc5tja: Yes, but you can use ghostscript to convert eps to png16m, which you _can_ then view on the web. | 21:35 |
| ZipCPU | Don't forget to make certain you have some number of text alpha bits set. | 21:37 |
| ZipCPU | kc5tja: Okay, so I tried it out, although I used Image-Magick instead of ghostscript. Here's the result: http://imgur.com/a/ZujY5 | 21:51 |
| ZipCPU | Commands used: inkscape -D -z --file=block-diagram.svg --export-eps=block-diagram.eps | 21:51 |
| ZipCPU | Followed by: convert block-diagram.eps -flatten block-diagram.png | 21:52 |
| ZipCPU | I'm sure you could do more with ghostscript--perhaps even to get the text to look better, but this was easy and simple. | 21:52 |
| kc5tja | I really wish Firefox and Inkscape would just bloody cooperate. I wouldn't have to go through these crazy-as-fsck gyrations just to get something that can display and print equally well. >:/ | 22:04 |
| ZipCPU|Laptop | kc5tja: I use this wonderful program called 'make' ... it makes the gyrations less painful. | 22:10 |
| kc5tja | No, it just automates the process. The pain remains. | 22:17 |
| kc5tja | I have to now maintain two sources of documentation, one for PDF, and one for the web, if I want to get good quality output. And that's just stupid in my estimation. | 22:17 |
| --- Log closed Mon Oct 17 00:00:00 2016 | ||
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