| --- Log opened Sun Oct 02 00:00:38 2016 | ||
| kc5tja | Only two instruction classes remain to be implemented: conditional branches and SYSTEM instructions. | 00:09 |
|---|---|---|
| -!- impihl is now known as imphil | 08:26 | |
| shorne | opencores.org seems back, but media wiki gone? http://opencores.org/or1k/Main_Page | 08:30 |
| shorne | openrisc ABI spec mentions "Structure and union arguments are passed as pointers." | 10:00 |
| shorne | Does anyone know any other ABI's that do this? It seems all others pass all data on the stack | 10:01 |
| shorne | I mean regs then stack | 10:01 |
| wallento_ | I roughly remember this was an issue before (specifically the difference between varargs and standard args) | 10:17 |
| Laksen | shorne, maybe Linux-PowerPC ABI | 10:18 |
| Laksen | Sparc | 10:18 |
| shorne | Laksen: thanks, Ill have a look | 10:33 |
| shorne | wallento_: yeah, I am just wanting to discuss in my orconf presentation about ABI strangeness and wanted to mention this as something that causes issues | 10:34 |
| shorne | related to my gdb work | 10:34 |
| wallento_ | we even had a vote three years ago at orconf | 10:49 |
| wallento_ | and the "don't break ABI compliance" won over the "but the others do it and some crappy code makes stupid assumptioms" won | 10:49 |
| wallento_ | I think it was xfw or so casting variadic to non-variadic function pointers | 10:50 |
| wallento_ | which crashed on OpenRISC | 10:50 |
| wallento_ | but stekern knows better, he had the headache back then IIRC | 10:50 |
| kc5tja | Holy **CRAP** opencores.org is WAY faster than I remember it being now. :) Pleasant surprise this morning. | 11:53 |
| ZipCPU | kc5tja: I'm wondering if open cores isn't being hosted on github now as a server, since once when they were | 15:12 |
| ZipCPU | setting up, I got a github error message. | 15:12 |
| kc5tja | I never knew they were hosted on Github. Seems like much too dynamic a site to be hosted there. | 16:33 |
| kc5tja | OMG. I've reached a milestone. An epic milestone. | 16:33 |
| kc5tja | Polaris Verilog is now ready to receive interrupt and trap support. | 16:33 |
| --- Log closed Mon Oct 03 00:00:39 2016 | ||
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