| --- Log opened Fri Jun 17 00:00:57 2016 | ||
| wallento | GeneralStupid: Computer Engineering ;) | 02:29 |
|---|---|---|
| wallento | SMDhome: of course it would be awesome to have an asic-proven core ready, and better testing and verification would be the key to this (beside actually taping it out) | 02:35 |
| wallento | but I slightly disagree with your colleagues. ARM cores are actually not that expensive and they actively promote it for small production volumes with good pricing, I think. There are hundreds of Chinese ARM SoCs with relatively small volumes in the market.. | 02:36 |
| SMDhome | wallento: so are there any steps taken towards verification? | 02:39 |
| wallento | I think we discussed it at least ;) | 02:54 |
| SMDhome | I have a short memory, sorry) | 02:58 |
| wallento | SMDhome: That was meant a bit sarcastical ;) | 06:03 |
| SMDwrk | wallento: someone has to write a detailed testing plan and then we can make tests based on it, right? | 07:08 |
| wallento | I think the first step is to have someone that really understands testing well | 07:09 |
| wallento | I only know some terms, but have no real idea to be honest | 07:09 |
| olof | Any DPI users? | 08:59 |
| -!- goyeld is now known as soiled | 09:19 | |
| ZipCPU | Does anyone have clock rate numbers for OpenRISC running on any Xilinx platforms? Both in terms of fundamental clock rate, and fewest clocks per instruction? | 09:22 |
| ZipCPU | I think I read 50 MHz at one time somewhere google'd and online ... | 09:27 |
| olof | I managed to synthesize a minimal mor1kx to ~200MHz on a Virtex-6, but I think 50MHz is pretty standard for our SoCs | 09:39 |
| olof | And I know that we have some CPI measurements from dhrystone other tools somewhere. stekern or bandvig might know more | 09:39 |
| ZipCPU | olof: I wasn't going to go as far as dhrystone for a benchmark. I was specifically looking for the fastest instruction clock cycle. Dhrystone gets ... confusing. | 09:42 |
| ZipCPU | Dhrystone depends upon cache's, branch execution delay, pipeline delays, compiler success ... it's a decent overall measure, | 09:43 |
| ZipCPU | but I was looking for something a touch more ... raw. | 09:43 |
| olof | Most instructions are single-cycle, if that's raw enough :) | 09:44 |
| ZipCPU | That's the raw I was looking for. | 09:44 |
| olof | I find DPI extremely confusing | 09:44 |
| olof | Or perhaps it's just how it's used in Pulpino | 09:45 |
| ZipCPU | "DPI"? Did you mean "CPI", or "Clocks per Instruction"? | 09:45 |
| olof | ZipCPU: Sorry. I'm talking about the method in SystemVerilog to call out to C code. (like VPI for verilog) | 09:45 |
| olof | or pli before that | 09:45 |
| olof | All these TLAs :) | 09:46 |
| ZipCPU | Ah ... topic change. ;) No problem. | 09:46 |
| ZipCPU | olof: Thanks for the quick answer, though: 50 MHz, most instructions take one clock, mor1kx. | 09:46 |
| olof | So, the DPI c file include as dpiheader.h, which is generated when the C file is compiled | 09:47 |
| olof | It seems like this is the way Modelsim wants to have it | 09:48 |
| olof | Xilinx xsim otoh creates the DPI lib first in the xsc stage, and later on, in the xelab stage we can generate the .h file. So including it from the C file makes no sense at all | 09:49 |
| ZipCPU | Not a Verilator day for you? | 09:50 |
| olof | ZipCPU: No, I've wanted to update the Pulpino cores for FuseSoC, but they started using DPI, and there isn't any DPI support in FuseSoC yet | 09:54 |
| olof | So I need to figure out how to do this in a nice way that works for all DPI-enabled simulators | 09:54 |
| olof | Right now it looks like the API will be pretty similar to VPI | 09:54 |
| ZipCPU | Ah! That makes more sense. | 09:54 |
| wallento | I did | 10:09 |
| wallento | ah, there is some more text :) | 10:10 |
| wallento | I haven't looked at it in detail, but we use DPI with ISIM and verilator in parallel in lowrisc | 10:11 |
| shorne | Hi all, I havent been talking much because of a few things, but still working on newlib and gdb patches for upstream... | 20:49 |
| shorne | This is a summary of gdb/newlib issues pointed out by the gdb testsuite | 20:50 |
| shorne | https://gist.github.com/stffrdhrn/f96fbc9c0a94b6299dd50fa1f79640c6 (I have been updating it) | 20:50 |
| shorne | I think for GDB the failures are not big, so we dont need more fixes (unless someone else wants to :)) | 20:50 |
| shorne | For newlib I want to fix the compiler issues, then we should be good to go (listed at the bottom of the gist) | 20:51 |
| shorne | in summary (newlib missing sys/mman.h, environ multiple defines, wait, rename. gettimeofday) | 20:52 |
| shorne | Chime in if you think we dont need to touch any of them | 20:52 |
| --- Log closed Sat Jun 18 00:00:58 2016 | ||
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