| --- Log opened Mon Jun 13 00:00:51 2016 | ||
| mor1kx | [mor1kx] olofk opened pull request #35: Remove empty parameter lists (master...master) https://github.com/openrisc/mor1kx/pull/35 | 07:10 |
|---|---|---|
| olof_ | imphil: Good thinking with the conditional filesets | 07:33 |
| mor1kx | [mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/5b10fe0343a59efe98fa7d9bf0fd5e6a75c3edf0 | 07:34 |
| mor1kx | mor1kx/master 5b10fe0 Olof Kindgren: Remove empty parameter lists | 07:34 |
| stekern | nice that github has added the possibility to do squash-and-commit pulls | 07:34 |
| repmovsd | I am looking for a disassembler for OpenRisc. | 07:36 |
| stekern | so you can merge single patches without getting a merge commit | 07:36 |
| repmovsd | Is there a way to make objdump work with it? | 07:36 |
| stekern | and merge pull requests that has "fix-up" commits in them | 07:36 |
| imphil | olof_, even better would be xilinx not having two major revisions in half a year of their MIG, but I guess that's wishful thinking | 07:38 |
| stekern | repmovsd: if you install a openrisc toolchain you'll get an objdump with that | 07:38 |
| imphil | olof_, seems to be impossible after years of development to have a relatively stable API for a memory interface. | 07:39 |
| olof_ | imphil: I can't believe that they're still doing that. I had the same problems four years ago, and was almost ready to forgive them now, because I thought they had learned | 07:39 |
| repmovsd | stekern: Thanks. Is there a working windows port? | 07:40 |
| olof_ | imphil: No, it's completely crazy. And in my experience they are sometimes subtly changing the behaviour of a signal or even reversing the meaning between two FPGA families | 07:40 |
| stekern | repmovsd: don't think so, easiest is probably to use a linux vm if you're a windows user | 07:41 |
| imphil | olof_, once they changed the polarity of the reset signal from active high to active low. fun debugging that. | 07:41 |
| olof_ | imphil: We should start a support group for MIG users | 07:41 |
| repmovsd | stekern: I see. I try to install the toolchain and see how it goes :) | 07:41 |
| stekern | imphil: really? they must really hate their users... | 07:41 |
| imphil | olof_, http://www.xilinx.com/support/answers/54025.html looks like there were "stable" years, but now they're picking up speed again. 2016.2 comes with v4.0 | 07:41 |
| olof_ | There have been some improvements in the open source controllers, but the problem is that the Vendor-generated ones is starting to contain a lot of undocumented primitives and stuff that you're not really supposed to know about | 07:42 |
| olof_ | I think a good compromise would be if they started supporting the DFI standard, so we could implement a proper controller, and they can keep their crazy proprietary nonsense on the phy side | 07:43 |
| olof_ | I know that Altera has been moving in this direction, but as usual, if one of the big FPGA vendors support a standard, the other one refuses to do the same | 07:44 |
| olof_ | Why doesn't my mor1kx start executing from OPTION_RESET_PC? Looks like it just tries to read from 0 | 07:57 |
| stekern | hmm, haven't seen that | 08:02 |
| olof_ | I've used signal tap now and see that it the fetch module enters the read state, but just asks for address 0 | 08:04 |
| wallento | is the reset correct? | 08:04 |
| olof_ | I'm a bit worried this is because I don't have a proper reset signal | 08:04 |
| olof_ | I'm just creating one with a shift reg | 08:04 |
| wallento | that should be okay usually, right? | 08:04 |
| wallento | because its synchronous IIRC | 08:05 |
| wallento | otherwise you need to create a pulse out of your reset | 08:05 |
| wallento | detect the falling edge of the reset and generate a pulse | 08:05 |
| wallento | I think oh! contains the building blocks for such things | 08:06 |
| olof_ | I already have those things. I'm using a synchronous release asyncronous set module | 08:07 |
| olof_ | But I don't have an external reset input | 08:07 |
| olof_ | ok, one step further. At least the PC is set to 0xf0000000 now | 08:34 |
| olof_ | Fuck yeah! It was a reset problem all along. mor1kx or some other core requires a reset to work | 08:45 |
| olof_ | And for some reason, my first attempt didn't work | 08:45 |
| ZipCPU | Is anybody building ORPSOC on an S6 these days? I'm looking for a LUT count ... | 13:47 |
| olofk | ZipCPU: We have builds for the Atlys board, and I have a WIP for the lx9 microboard | 15:51 |
| ZipCPU | olofk: Here's what I'm trying to do ... as part of putting an abstract together, in the hopes of presenting at ORCONF, I really need something to compare with. | 15:52 |
| ZipCPU | I can make various ZipCPU builds, but I'd like to compare their LUT counts with ... other options. | 15:52 |
| ZipCPU | Brakefields work gives me some wonderful point data, but ... it's just a spreadsheet. It's hard to compare apples to apples. | 15:53 |
| ZipCPU | I'd like to compare LUT counts between the ZipCPU and ... other CPU's. But ... LUT counts with divide instructions? Multiply instructions? Pipelines? MMUs? Instruction caches, of what size? | 15:53 |
| ZipCPU | The options seem endless. | 15:53 |
| ZipCPU | Still ... where would I find a build for an Atlys or lx9 board. I might find either (or both) instructive. | 15:54 |
| olofk | Oh yes. The double-edged sword of configurability | 15:54 |
| ZipCPU | :P | 15:54 |
| olofk | We have been talking about creating a OpenRISC base system. Something perhaps with a sane configuration of mor1kx, 32MB RAM, gpio, UART, SPI and i2c | 15:55 |
| ZipCPU | Sigh ... that's another difficulty. How do you compare in the presence of (different) peripherals? | 15:56 |
| olofk | That would give us something of a yard stick at least | 15:56 |
| olofk | Most modern synthesis tools are at least capable of giving you LUT count for each sub module. | 15:57 |
| ZipCPU | It's a start, although ... every FPGA board I've worked on has had Flash and block RAM, not as many have had proper DDR RAM. | 15:57 |
| ZipCPU | True, although I've learned not to trust XST with ISE. It leaves too much logic at the top. | 15:57 |
| olofk | For many years, Xilinx themselves told people to use Synplify instead, so you're not alone in not trusting xst :) | 15:58 |
| ZipCPU | Does mor1kx offer internal peripherals as well? My initial version of the ZipCPU had a ZipSystem associated with it that offered 3x timers, an interrupt controller, 8x counters, and some watchdog timers. | 15:59 |
| ZipCPU | I had to trim down later when that was too much for some applications. | 15:59 |
| olofk | You can remove some things, but the or1k spec defines at least the interrupt controller and timer iirc | 15:59 |
| ZipCPU | Makes sense ... it is kind of hard to get a interval timer driven multi-processing system running without those two. | 16:01 |
| olofk | stekern can probably correct me here, but I think that removing caches, MMUs, FPU and divider will get you close yo minimum size | 16:01 |
| ZipCPU | If you remove all caches, are you still pipelined? | 16:01 |
| olofk | Not sure actually | 16:02 |
| ZipCPU | In my case, removing all caches removes the pipeline contention logic as well. | 16:03 |
| olofk | You can configure the wishbone buses with our without bursts, so in theory, I guess you could have a 8 word cache just to make a burst access to the memory | 16:03 |
| olofk | But I would have to check the implementation (or preferably ask someone who knows) to be sure | 16:04 |
| olofk | Trying to think of all things that are great with FuseSoC so I can put it on my poster for the RISC-V conference | 16:05 |
| Laksen | How do you do the interconnect stuff or doesn't it do that anymore? | 16:09 |
| olofk | Laksen: It doesn't do any automatic interconnects. I think it's too complex to handle inside of FuseSoC. My idea is instead to use external tools that can do this, for example with IP-XACT descriptions | 16:11 |
| olofk | Kactus2 is getting there, but I would like to have a command-line flow as well, so it can be done as a step during the build process | 16:12 |
| olofk | FuseSoC (or rather some of the cores that is FuseSoC-compatible) does however have some utilities to make it easier to create interconnects for Wishbone-based systems | 16:13 |
| Laksen | Okay | 16:13 |
| olofk | It currently generates verilog code for the interconnect, and the next step is to also generate an IP-XACT description so that it can be dropped directly into a IP-XACT enabled tool | 16:13 |
| ZipCPU | olofk: In my minimum configuration, I can get the CPU down to 1215 LUTs, and a minimal SoC that fits in a Spartan LX4 in 2,220 LUTs. | 16:18 |
| olofk | ZipCPU: OpenRISC isn't all that small, but it would be interesting to compare it to picorv32 | 16:21 |
| olofk | Have you tried building zipcpu for the iCE40 devices? | 16:21 |
| olofk | SMDhome: | 16:22 |
| olofk | sorry. Slipped on the keyboard | 16:22 |
| ZipCPU | olofk: No, I've never tried building the ZipCPU for anything but Xilinx. It should build, though, I haven't used any Xilinx specific primitives. That said, switching vendors is always an adventure. | 16:27 |
| olofk | ZipCPU: Yes, it is. But FuseSoC makes it easier to port designs to new targets | 16:29 |
| olofk | At least it says so on the poster :) | 16:29 |
| ZipCPU | (Looking up picorv32 now ...) | 16:38 |
| ZipCPU | Gosh ... 750 LUTs? | 16:41 |
| ZipCPU | Okay, it says 750-2000 ... and that's a broad range, but still ... | 16:43 |
| olofk | You can build picorv32 with FuseSoC if you want to try it out :) | 16:51 |
| ZipCPU | Thanks! I'm still digging through the RISC-V spec to find out what's different, though. | 16:52 |
| olofk | I think they put a lot of thought and effort into streamlining the ISA. Many of the ideas there is the same that we had for a upcoming or2k ISA | 16:56 |
| ZipCPU | Well, the spec certainly reads like they put a lot of thought into it--especially since it records why they made their various choices. | 16:56 |
| Laksen | Anyone have experience using IP-XACT stuff from Vivado in Kactus2? | 16:57 |
| olofk | Yes. I heard it's a great read in that regard. Haven't dug too deep myself | 16:57 |
| Laksen | I can't get it to find my components :( | 16:57 |
| olofk | Laksen: Yes, I know that the guys from Antmicro are using a combination of Vivado and Kactus for the Axiom camera project | 16:57 |
| olofk | I have managed to get Kactus2 to read some Xilinx IP, but unfortunately the compatibility isn't very good. Both tools define their own tags that the other don't understand | 16:58 |
| olofk | And starting with Kactus 3, they have switched to using only IP-XACT 2014, which Vivado doesn't handle | 16:59 |
| Laksen | Ahh | 16:59 |
| olofk | So it's a bit of a mess | 16:59 |
| Laksen | Sounds like it :( | 16:59 |
| olofk | But Kactus 2.8 can at least read some Vivado ip | 16:59 |
| Laksen | Yeah, I remember it sort of being able to use Logicore ip | 17:00 |
| olofk | Yeah. I like IP-XACT because it's the best hope we have for a vendor-independent standard, but the standard itself is horrible in many places | 17:00 |
| olofk | But FuseSoC can read IP-XACT 1.4, 1.5, 2009 and 2014 :) | 17:01 |
| Laksen | Yeah it's a great idea, but pretty extreme | 17:01 |
| Laksen | Hehe how much of the standard does it support? | 17:01 |
| olofk | FuseSoC knows enough to read filesets from IP-XACT files, which is the only thing that it currently uses from IP-XACT | 17:02 |
| olofk | That works quite well | 17:02 |
| olofk | The internal library that FuseSoC uses to read IP-XACT (https://github.com/olofk/ipyxact) handles also most of the register parts and some of the bus interfaces, but FuseSoC can't use that yet | 17:03 |
| olofk | Time to sleep now | 17:04 |
| Laksen | I might have to stress test it :) | 17:06 |
| Laksen | Working on this thing right now: http://j-software.dk/riscv-ip-xact.png | 17:07 |
| olofk | aha | 17:08 |
| olofk | vscale is supported in FuseSoC, btw | 17:08 |
| olofk | :) | 17:08 |
| olofk | I think there are cores for five different risc-v implementations in the standard core library | 17:08 |
| Laksen | Hehe guessed it was. I just became inspired to try out some Vivado packaging :) | 17:08 |
| olofk | If you have an IP-XACT file for vscale, I'm happy to take a look at it to showcase the FuseSoC IP-XACT integration | 17:09 |
| olofk | There aren't many good examples right now | 17:09 |
| Laksen | I can for sure send it, but I haven't tested it yet. That's why I'm sad only Xilinx has this nice a flow | 17:09 |
| Laksen | Got no series 7 boards at home :( | 17:09 |
| olofk | FuseSoC makes it easy to test your designs with multiple simulators | 17:10 |
| * olofk is turning off marketing mode | 17:11 | |
| Laksen | Hehe | 17:12 |
| --- Log closed Tue Jun 14 00:00:52 2016 | ||
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