| --- Log opened Wed May 25 00:00:22 2016 | ||
| olof | shorne_: I think it's fine to apply the patches. Hope to find time for that today | 03:25 |
|---|---|---|
| -!- shorne_ is now known as shorne | 05:17 | |
| shorne | olof: cool | 05:18 |
| olof | wallento: I'm pushing your patch that sanitizes names, but I have been changing it a bit, since I've done some heavy refactoring lately | 08:25 |
| SMDwrk | Has anyone made any verification for openrisc? | 12:40 |
| olofk | SMDwrk: What kind of verification? We have plenty of testcases, but no formal verification | 14:39 |
| olofk | Is OpenCores svn down again, or is the problem on my side? | 15:15 |
| bengardiner | Hi all, I've got a question about Cyclone III FPGA JTAG -- I'm guessing that you guys have expertise here. I've got a board with a Cyclone III that I've inherited. I'm pretty sure I've got test points for JTAG properly identified. When I try to IDCODE or BYPASS I'm getting all 1's (0xff...). I noticed that in Application Note39 | 21:13 |
| bengardiner | https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an039.pdf it is possible to disable JTAG with bootstrap pin values. My probing of the voltages on the PCB suggests that it is disabled this way. So... I'm wondering 1) is there a recomended way to re-enable JTAG? pull one pin /away/ from the states in table 12? 2) could there be | 21:13 |
| bengardiner | another reason? other than the disabled BST -- or that I've got the wrong pads :) ? | 21:13 |
| --- Log closed Thu May 26 00:00:23 2016 | ||
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