IRC logs for #openrisc Wednesday, 2016-04-06

--- Log opened Wed Apr 06 00:00:08 2016
olofkAh.. fixed the or1200-generic problems. Hope I will never have to touch that again02:39
olofkAnyone with the sockit board? stekern?04:01
stekernmmm?04:02
olofksockit is the last user of the ram_wb component. I'd like to replace that with wb_ram04:21
olofkBut I don't have my board, so I can't check it04:21
olofkAnd I'm not really sure what it's used for. It says internal SRAM04:22
olofkHmm... does icarus support DPI? Anyone tried?04:30
olofkDoesn't like like it :/04:38
stekernI think I just used it before I got the DDR working, to debug the DDR04:39
olofkstekern: Oh, so if I replace it with a wb_ram component it probably won't matter since it's not really used anyway :)04:45
olofkNice. Running dpi with modelsim was easy04:47
stekernolofk: right04:49
olofkstekern: I'lll just do it then, so I can retire ram_wb04:57
wallentoolofk: I also did some SRAM and DPI stuff05:00
wallentobut more related to verilator05:01
wallentoits a variation of what I did also for OpTiMSoC: https://github.com/optimsoc/sources/blob/master/tbench/dm/system_2x2_cccc/tb_system_2x2_cccc.cpp05:01
wallentoI combined it with the verilator support stuff in orpsoc-cores05:02
wallentoI will push it later today I hope05:02
wallentoIt allows to set the memory file as a parameter: --meminit=<binfile>05:05
wallentohttps://github.com/optimsoc/sources/blob/master/src/soc/hw/sram/verilog/sram_sp_impl_plain.v#L12105:05
wallentothe parameter changed to string recently: https://github.com/wallento/verilator/commit/c5332de86d02917b5a447ecef1328de6a07c790405:06
olofkwallento: Why do you need a DPI task for that?05:14
olofkI just do it by setting the mermory. Works for all simulators05:15
olofkFor example https://github.com/openrisc/orpsoc-cores/blob/master/systems/mor1kx-generic/bench/verilator/tb.cpp#L8905:16
wallentobecause thats the recommended way05:19
wallentothe memory is not guaranteed to be accessible without DPI, right?05:19
wallentolike in verilator you need to put a verilator_public to it05:20
wallentohttps://github.com/openrisc/orpsoc-cores/blob/master/cores/wb_ram/rtl/verilog/wb_ram_generic.v#L1205:22
wallentothe mem variable may also accessible in other simulators, but there is nothing that prevents a compiled simulation to make it inaccessible05:23
olofkHmm.. I see your point05:25
olofkI think it should be ok anyway since we always access it in the other sims, so it can't be optimized away, but there's always a risk for that05:25
wallentoyeah, it should be okay generally05:26
wallentoI would only expect VCS or so to do anything to it05:26
wallentohow do you do it in modelsim?05:26
wallentoor icarus?05:26
wallentoI have actually never tested it with anything but verilator05:27
olofktested what?05:31
olofkDPI?05:31
olofkor do you mean access memory?05:32
wallentoaccess the memory05:34
olofkLike this https://github.com/openrisc/orpsoc-cores/blob/master/systems/mor1kx-generic/bench/verilog/orpsoc_tb.v#L4605:36
olofkUsing the elf-loader in this case05:36
wallentoI see05:53
wallentothat should also work in any case as DPI05:53
wallentobut the DPI solution is a bit more flexible05:54
wallentoit can initialize any number of RAM instances05:54
wallentojust by their name05:55
wallentowith an SV-wrapper it always needs to be adapted to the system05:55
wallentobut I will need to test it with modelsim, xsim and icarus05:55
wallentohttps://github.com/optimsoc/sources/blob/master/src/host/sim/src/VerilatedControl.cpp#L6605:56
wallentothats where I initialize all memories05:56
shorneHi all, I spent some time reviewing and testing my patch for memblock.  I think its ok I just sent a mail to the list06:13
shornelet me know if there are any questions06:13
shorneSame is available here https://github.com/stffrdhrn/linux/tree/openrisc06:14
olofkAnyone with a riscv64 tc, who can compile some stuff for me?12:16
olofkwallento: Would it be hard to set up automatic build of the riscv toolchains too? Don't have time or diskspace for more toolchains on my laptop12:54
mafmolofk: I can give it a tri, if it's a relatively uninvolved thing to get compiled14:43
mafmtry* even14:43
wallentoolofk: I actually stopped jenkins and trigger builds manually on my server now17:01
wallentoI can build one and upload somewhere17:01
olofkwallento: That would be nice17:23
olofkIn the meantime, I'm looking to create riscv.bin as described here https://github.com/terpstra/opa/blob/master/demo/build.sh17:24
olofkDon't need the lm32 version though17:24
olofkStarted looking at the toolchain build instructions for riscv17:24
olofkThey propose installing the toolchain to a subdirectory of the build directory. Isn't that a bit fucked up?17:25
olofkor maybe not. It makes a bit sense for single user systems17:26
wallentoyeah, its kind of developer centric17:32
olofkI just want to be able to compile a simple riscv program17:34
olofkAlready have the 32-bit tc installed17:34
olofkHow does llvm work btw? Do you only need one clang for all arches?17:44
olofkok, got it installed myself17:53
--- Log closed Thu Apr 07 00:00:10 2016

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