| --- Log opened Mon Dec 14 00:00:01 2015 | ||
| olofk | andrzejr: I pushed a patch to FuseSoC's xsim support to allow simulating stuff that contains $clog2 | 22:01 |
|---|---|---|
| andrzejr | good, thank you | 22:02 |
| olofk | You need to set file_type = SystemVerilogSource in the verilog section for those cores. I'll push a patch for orpsoc-cores that adds this to wb_bfm-1.0 | 22:13 |
| olofk | As a side note, it is now also possible to set file type and if the file is an include file for each file by adding file.v[is_include_file] or file.v[file_type=verilogSource] | 22:15 |
| olofk | Multiple options are comma-separated. e.g. file.v[is_include_file, file_type=systemVerilogSource] | 22:15 |
| olofk | This is unfortunately not backwards-compatible, as older versions of FuseSoC will read the whole string as a single file | 22:16 |
| olofk | As usual FuseSoC documentation is available at http://www.juliusbaxter.net/openrisc-irc/ :) | 22:28 |
| olofk | Hmm... just realized that spaces aren't allowed so it should be file.v[is_include_file,file_type=systemVerilogSource] | 22:33 |
| --- Log closed Tue Dec 15 00:00:02 2015 | ||
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