IRC logs for #openrisc Wednesday, 2015-09-23

--- Log opened Wed Sep 23 00:00:17 2015
--- Day changed Wed Sep 23 2015
_franck__andrzejr: what signal did you hooked up here: https://github.com/openrisc/orpsoc-cores/blob/master/systems/atlys/rtl/verilog/orpsoc_top.v#L408 ?07:28
-!- orsonmmz|away is now known as orsonmmz07:28
andrzejrhi _franck_, BSCANE2.SEL07:29
_franck__BSCAN code in openocd does not have any instruction to enable the debug core (something like this in altera VJTAG: https://github.com/openrisc/orpsoc-cores/blob/master/cores/altera_virtual_jtag/altera_virtual_jtag.v#L107)07:30
andrzejrbtw, I've just found I was using a different version than the default one in orpsoc-cores, afair from git master branch07:30
andrzejrI see, thank you, will try that07:31
_franck__a different version of what ?07:31
andrzejrof adv_debug_sys07:31
_franck__may be you should try to force debug_select_i to '1'07:31
_franck__or at least output this signal to a led to see its level07:32
andrzejris it possible to debug the jtag tap in simulation? I can access BSCANE2 via glbl instance but do we have any simulation model for "jtag master"?07:32
andrzejrwill do that, I have to leave for work soon07:32
_franck__yes we can connect openocd to  a simulated soc, just have to remember how :)07:33
_franck__andrzejr: you need to use this interface http://repo.or.cz/openocd.git/blob/HEAD:/tcl/interface/jtag_vpi.cfg07:36
andrzejrIf we can define a sequence of JTAG commands to send it should be easy to write a simple bfm model.07:36
andrzejrI've got it already (from atlys) but haven't tried if it still works07:37
olofkandrzejr: I guess the problem would be that you might need ISIM or XSIM with the BSCAN model, and none of those support vpi10:19
olofkGeneralStupid: Don't worry. You're not forgotten :)10:23
maxpalnhowdy all, after a few months of absence - I am back on the ORPSOC port to our eval board :-)15:14
poke53281wb15:15
maxpalnI have a few housekeeping things to do first though - I have pulled in a new version of the MOR1KX for ages and my simulation test suite also hasn't been updated since I was still working on the OR1200!!!!15:15
maxpalnpoke53281: thx15:16
maxpalnI remembered that in my implementation I had switched out the RTL multiplier for an instantiation of our hard coded multiplier block. I switched 'FEATURE_MULTIPLIER' to PIPELINED and rebuilt the design but it doesn't work. I'm just trying THREESTAGE - but should these all work when booting Linux?15:46
maxpalnI suspect this is a synthesis issue (the same one that caused me to instantiate one of our multipliers directly. But I thought it worth investigating.15:51
andrzejrmaxpaln, what board?17:45
andrzejrolofk, fortunately BSCANE2 is not encrypted.17:48
olofkandrzejr: Ah, that helps18:45
olofkmaxpaln: HAven't really played with the different multiplier options. Have you tried them in simulations?18:46
olofkAnd I hope for god's sake that you have switched away from ORPSoCv2 to FuseSoC now ;)18:46
-!- orsonmmz is now known as orsonmmz|away19:37
--- Log closed Thu Sep 24 00:00:57 2015

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