| --- Log opened Tue Aug 18 00:00:05 2015 | ||
| latif | hi all.. As I told you before I am trying to boot orpsocv3 from spi flash on atlys board.. | 11:46 |
|---|---|---|
| latif | I have added a led blink app to bootrom.S code to understand whether it is working correctly.. | 11:47 |
| latif | The result is not positive.. Niether orpsocv2 nor orpsocv3 could not run it. I mean the booting is successfull but the leds are not blinkjing.. Before, I managed to run such app by using a C code (then turning it to a mcs file) on orpsocv2 (not on orpsoc v3- tried but not managed to run).. | 11:50 |
| latif | So I think there may be a pproblem with bootrom.S | 11:51 |
| latif | or it is a problem related with atlys board | 11:51 |
| _franck__ | latif: is your boot address correct ? | 12:34 |
| _franck__ | .OPTION_RESET_PC (32'hf0000100) | 12:34 |
| latif | I think so.. because I have managed to boot orpsocv2 before | 12:35 |
| _franck__ | does it match what's in wb_intercon.conf in rom section ? | 12:35 |
| _franck__ | ah sorry you are using an existing system so it should be correct | 12:36 |
| latif | yes.. It should be.. because I did not change anything on rom.v or wb_intercon.conf.. Just added the bootrom code into the rom.v | 12:38 |
| _franck__ | where did you edit the rom.v file ? because it is maybe overwritten while building with fusesoc | 12:39 |
| _franck__ | to be sure put some garbage in the file you edited to see if Xilinx complains | 12:40 |
| latif | franck... I have tried it before.. I get a xilinix project and add it all files. Xilinix complains if you do anything wrong.. | 12:47 |
| _franck__ | I didn't mean you open the Xilinx project, just do "fusesoc build atlys" | 12:49 |
| _franck__ | to see if you're compiling with your midification included | 12:49 |
| latif | Aha.. I see.. But the answer is still yes.. I mean for example if you change a module (add a stupid thing in it) and run "fusesoc build atlys" then Xilinxs complains you about that | 12:55 |
| _franck__ | " booting is successfull" -> how do you know that ? | 12:56 |
| latif | FRANCK...when I power on th board after loadin mcs, a done led on board is blinking after 3-4 seconds.. like the other succesfull triyings.. | 13:04 |
| _franck__ | I guess done means "FPGA configured" (who's blinking this led ?) it doesn't mean the CPU start executing the code in the rom | 13:11 |
| latif | _franck_... yes you are rigth.. I can not say it as an evidince.. | 13:20 |
| blueCmd | stekern: do you have any synthesis statistics on mor1kx on your Zynq? | 14:22 |
| blueCmd | how much did it use etc | 14:22 |
| blueCmd | I'm considering buying something with a Zynq Z-7020 in it, but I have no sense of how big the FPGA is | 14:22 |
| -!- Netsplit *.net <-> *.split quits: _franck_, bentley`, jeremybennett, hansfbaier | 14:59 | |
| -!- Netsplit over, joins: hansfbaier, jeremybennett | 15:12 | |
| stekern | blueCmd: sorry no, I've never got around to play with mor1kx on the zynq | 15:27 |
| andrzejr | blueCmd, it will fit easily | 18:10 |
| blueCmd | andrzejr: right, but what more? I'm trying to get an estimate of how "big" that version is | 18:11 |
| andrzejr | 7020 has 85k logic cells, I'm currently using Artix7 (same fabric) with 100k cells and the whole orpsoc with capuccino and DDR2 i/f (the biggest contributor) takes ~20%. | 18:11 |
| blueCmd | I have a Kintex that's like *gigantic*, 64 OpenRISCs without a problem :P | 18:11 |
| blueCmd | Cool, thanks! | 18:11 |
| andrzejr | Mor1kx itself takes 1499 slices (out of 15860) and 15 BRAM blocks (~9%). Zynq is only slightly smaller. | 18:21 |
| andrzejr | olofk, how to do cdc with buses? | 22:08 |
| andrzejr | I have two synchronous (fixed phase offset) clocks: wb_clk and ui_clk (generated by dram i/f) - synthesis is fine, simulation in most cases too, so it looks like the autogenerated timing constraints are OK | 22:10 |
| andrzejr | but in one case the simulation enters a combinational loop, not sure if that's because of my error or if making such cdc is a bad idea | 22:11 |
| andrzejr | for obvious reasons I want to avoid asynchronous cdc | 22:12 |
| andrzejr | sorry, the error is caused by something else | 22:23 |
| --- Log closed Wed Aug 19 00:00:06 2015 | ||
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