| --- Log opened Fri May 29 00:00:10 2015 | ||
| olofk | blueCmd: Ah yes. I think there is a bug that reports the two first transactions as invalid. | 10:29 |
|---|---|---|
| olofk | yep. Someone (I?) should file a bug report for that | 10:49 |
| olofk | stekern: I'm planning to add some basic qip support for the FuseSoC quartus backend, and I see that there already is something like that in the qsys parts. Do you remember the flow here? | 13:38 |
| blueCmd | olofk: https://github.com/bluecmd/wb-axi/blob/master/src/wb_to_axi4lite_bridge.v simple enough | 13:41 |
| blueCmd | I'll do some more validation testing with an actuall DDR3 controller is my plan, then I'll probably try it out in real world, if it works I might look into adding bursting | 13:42 |
| blueCmd | I have no plans for AXI -> WB at this point, I see limited reasons to use it (DMA and using AXI based CPUs comes to mind) | 13:43 |
| blueCmd | olofk: do you think that's feasible? | 13:43 |
| blueCmd | oh right, and implement my own axi4-lite -> axi4 converter instead of the Xilinx one I use today. | 13:44 |
| blueCmd | that should allow wb_intercon to be able to connect any axi4-lite and axi4 memory/peripheral to a Wb interconnect | 13:44 |
| olofk | blueCmd: Awesome. I like the code | 13:46 |
| olofk | And as you say, there is little reason to convert in the other direction | 13:46 |
| olofk | oh well. Actually, there are some use cases for that, but anyway | 13:46 |
| olofk | blueCmd: Looking at the code now. You should drive the clocks in testbench.v instead of setting them with a modelsim tcl script | 13:55 |
| blueCmd | olofk: yes. I'm lazy though | 13:58 |
| olofk | Lazy is good | 13:58 |
| blueCmd | olofk: but, since I don't know anything behind the "why". why? | 13:59 |
| blueCmd | I agree that it's nicer, but any arguments? | 13:59 |
| olofk | Well, you probably want to run it in other simulators than modelsim | 13:59 |
| blueCmd | this specific one, not likely - since it's dependent on compiled sim libs, I haven't researched if it's possible to compile Xilinx IPs to verilator | 14:00 |
| olofk | Probably not, but it should work fine with Icarus | 14:01 |
| olofk | and synopsys VCS, Xilinx ISIM, Xilins XSIM | 14:02 |
| blueCmd | that's nice | 14:02 |
| olofk | Which modelsim version are you using btw? | 14:03 |
| blueCmd | 10.2c | 14:03 |
| olofk | Is it the PE or DE version? | 14:04 |
| stekern | olofk: what do want to know? | 18:31 |
| GeneralStupid | c? Nice i only have 10.,2 | 19:01 |
| olofk | stekern: How are the qip files created? Are the generated when you run some script with the .qsys file as input? | 22:17 |
| --- Log closed Sat May 30 00:00:12 2015 | ||
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