| --- Log opened Sun May 17 00:00:53 2015 | ||
| olof | Hello, can someone help? How exit from asm program? I use or1k-elf-as <file_name.o> -o <file_name.s> then or1k-elf-ld <file_name> -o <file_name.o>. After all i use "fusesoc sim ..." and that is stop at load words, program in c load and run normally | 15:15 |
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| GeneralStupid | strg c ? | 15:36 |
| GeneralStupid | :) sorry, i dont know | 15:36 |
| GeneralStupid | iam just bored, going home by train atm | 15:37 |
| GeneralStupid | and hate it :) its full or is heavy loaded better? | 15:38 |
| latif | hi all, I am trying to use OrpSocV3 with bootrom.v but it s not working on Fpga.. Anyone can help me or give any idea?? Olofk, hesham, stkern..?? | 18:37 |
| latif | I am including bootrom.v to the rom.v and then generated .bit file of orpsocv3.. Then, I am compiling an easy C code like test witth or1k..then obj-copy and bin2binsizeworld... Then I am generating a mcs file by using orpsoc_to.bit and the ledtest_size.bin.. At the and I am loading it to SPI flas on my atlys board..programming succesfuly..but it is not working...leds didnot ligt up.. | 18:42 |
| bandvig | latif: As I remember you tried to do that with orpsocv2. Am I right? | 18:58 |
| latif | bandvig: yes.. you are rigth... It is working with orpsocv2..no problem.. I am trying to do same with V3 but I could not :( | 19:00 |
| bandvig | latif: do you use tool chain from orpsocv2? | 19:03 |
| latif | no.. I am using my own-installed toolchain.. I installed it from the webpage.. http://opencores.org/or1k/OpenRISC_GNU_tool_chain | 19:05 |
| bandvig | for both orpsocs? | 19:08 |
| latif | yes.. | 19:14 |
| bandvig | ok, it looks like a problem with SoC orpsoc_to.bit? Are you sure you use latest version of ORSoC components (I don't remrmber how to force fusesoc to update cached cores and run rebuild)? | 19:18 |
| latif | I dont know also.. I have just use fusesoc 2 days ago.. It downloaded the rtl files for atlys and the started to run xilinix.. tjhen it generated the bit file.. after that I add bootrom.v and include it to rom.v and REGENERATED the bit file.. | 19:26 |
| bandvig | well, it looks like you sources are fresh enough. But I use old rtl for all components excluding mor1kx. And perhaps there are hand-made modifications in my local copy of SoC top level. So it could be quite difficult to find your problem. | 19:32 |
| bandvig | Any case, first of all. Could you look in design log (stekern or olofk are able to point right place) and that all time constrains are met? | 19:39 |
| bandvig | Periodically we face with routing proble for 100MHz clock on the board. The workaround is to open atlys/rtl/verilog/include/orpso-defines.v; comment `define VGA0 and rebuild bit file. | 19:40 |
| latif | bandvig: I came accross place and route problem but then I solved it thanks to olofk.. I succesfully generated bit file (I think :) ) .. | 19:45 |
| bandvig | latif: Excuse me. I'm going to sleep. I hope, stekern or olofk continue helping you today. By. | 19:53 |
| latif | Thank you sop much bandvig by.. | 19:54 |
| olofk | latif: You are using an Atlys board, right? | 20:06 |
| --- Log closed Mon May 18 00:00:54 2015 | ||
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