IRC logs for #openrisc Friday, 2015-02-20

--- Log opened Fri Feb 20 00:00:49 2015
mor1kx[mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/fee34915756a1feb5beceff1fba50f6ee3f2b10f03:22
mor1kxmor1kx/master fee3491 Stefan Kristiansson: cappuccino: add support for l.msync...03:22
olofkWhen I woke up today I realized just how great a serial bootloader would be06:36
olofkstekern: I see that mor1kx support msync now :)06:36
olofkpoke53281: Hopefully, I should just be able to put links or lynx in my initramfs and run it, right?06:50
wallentostekern: nice one the msync!08:04
poke53281olofk: Almost, you need musl as well. And probably ncurses09:03
poke53281And openssl I guess.09:03
poke53281static binaries are so ancient :)09:04
stekernolofk: yup, interrupt handler has finished, back to adding vm support to the lk or1k port ;)09:15
Me1234_olofk: 0xb0000000:0001000012:34
olofkMe1234_: I'm not entirely sure what you just wrote :)12:37
Me1234_olofk: output of command x 0xb0000000 in GDB. 0xb0000000 is the SPI core address.12:44
poke53281http://2.bp.blogspot.com/_I182g1bK2Yw/TIwlCNFT9aI/AAAAAAAABPM/idRUu9vvJjg/s1600/WTF.GIF12:45
poke53281reminds me of the mysterion message of starflight, which turns out to be a phone number of one of the developers. :)12:45
Me1234_olofk: I am trying to connect old SPI core to ORPSOCv312:45
Me1234_olofk: Is this config in wb_intercon.conf ok?12:51
Me1234_[slave spi0]12:51
Me1234_datawidth=812:51
Me1234_offset=0xb000000012:51
Me1234_size=812:51
olofkMe1234_: And 0xb0000000 is where it's mapped in orpsocv2?12:52
Me1234_olofk: I have checked, it is same for ORPSoCv2 and ORPSoCv312:57
olofkcool. And your wb_intercon.conf looks good. Did you regenerate the verilog files?12:59
olofkBut since you can read the registers at 0xb0000000 I guess that it should be ok. Otherwise you would get an error13:00
Me1234_olofk: It is not my wb_intercon.13:01
Me1234_olofk: I only wanted to ask if everything is ok with size13:02
Me1234_olofk : It is a default orpsocv3 wb_intercon.conf13:02
Me1234_olofk: If I read out of ram and peripherals, for example13:09
Me1234_(gdb) x 0x200000113:09
Me1234_0x2000001: 0x4848484813:09
Me1234_olofk: No errors occur?!13:09
Me1234_olofk: And read value is non-zero. Is it wb_intercon bug?13:10
Me1234_olofk: After restart it is13:16
Me1234_(gdb) x 0x200000113:16
Me1234_0x2000001: 0x0000000013:16
olofkhmm...13:20
olofkIf this was an access from the CPU you would get both alignment exception and bus error I guess13:21
olofkDon't think it's a bug in wb_intercon.conf, but I'm not sure how the debug interface handles errors13:22
olofkCan you for example write something to address 0x0 and read it back after you have tried to access 0x200000113:22
Me1234_olofk: Am I writing to memory the right way? set {char}0x00000000 = 4213:56
Me1234_olofk: I set 0x0 to 42, try to read from 0x2000001, read 0x0 and get 42.13:59
juliusbolofk: hey man, not sure if you've mentioned this already, but are you planning on getting a Google summer of code program in this year at all for FuseSoC or something related to it?14:13
olofkjuliusb: Actually, Alex approached me with some FuseSoC ideas from the lowRISC side14:14
olofkI would love to have some OpenRISC projects, but I don't want to run it alone14:15
juliusbdeadline is today right?14:16
juliusbfor organisations at least14:16
juliusbwhat were you thinking on the OR front?14:16
olofkjuliusb: We got this from last year opencores.org/or1k/OR1K:FutureWork14:23
olofkUpdated it slightly a few weeks ago14:23
olofkActually, I see that VDSO is on the list. That one's done now14:24
Heshamolofk: According to the web-page, Linux is not the only OS that's running on OpenRISC. Last year GSoC project [1] provided an RTEMS port that works on or1ksim.14:56
Hesham[1] https://devel.rtems.org/wiki/Projects/GSoC/OpenRISC14:56
Me1234_Does newlib have sleep function? Or usleep?15:03
Me1234_ 15:04
Me1234_Or do I need to use the timer?15:05
wallentoHesham: I started putting it on the new website15:17
wallentoAre you planning to wrap up your tutorial?15:18
wallentohttps://openrisc.github.io/software.html#RTEMS15:18
Heshamwallento: Which website?15:18
wallentoI will complete the information on the cross compiler and kernel15:18
HeshamAh thanks, I have some blog posts15:19
wallentoand there is also a release build of the toolchain: http://lis.ei.tum.de/pub-download/openrisc-builds/or1k-rtems/15:19
wallentoI also comitted a patch to rsb recently that changes binutils to upstream 2.2515:19
wallentoI also got RTEMS to build (only a slight change to your blog: bsp is or1ksim and not or1k_or1ksim)15:20
HeshamGreat15:20
wallentobut I cannot run it on the de0_nano system, some UART issue it seems15:20
wallentothis is where I was last monday and did not find time until now unfortunately15:20
HeshamI didn't reach the FPGA implementation part15:20
wallentoIts maybe just a different BSP15:20
wallentobut I will have a look at it next week15:21
HeshamI actually tried hard to get OpenRISC on my Atlys board but couldn't15:21
HeshamSomething relates to DDR2 IIRC15:21
HeshamBut great work wallento, would you need some help writing a tutorial for how to run RTEMS on or1ksim?15:22
HeshamI intended to write one, but I got busy15:22
wallentoHesham: That would be nice15:54
wallentoI also started some stuff, but did not finalize it. It's straight forward from your blog posts, but with some slioght changes aber upstream15:55
HeshamOK, I'll try to write some simple blog posts and tell you then15:59
HeshamHave you managed to run OpenRISC on de0_nano? Baremetal?15:59
olofkHas anyone had problem with ethmac under Linux? I'm getting a lot of dribble nibble, packet dropped and wrong CRC messages in Linux16:41
olofkaha. Seems like maxpaln had this problem a while ago. Probably need to force it to not use 1gbps16:57
olofkAhh.. I was hoping for a slightly better solution :( http://juliusbaxter.net/openrisc-irc/%23openrisc.2014-01-02.log.html#t16:2517:27
Me1234Is slave selects register in simple_spi (default ORPSoCv3) b0000000 + 420:41
olofkMe1234: Looks like it. There's an interesting thing to note here though20:57
olofkThe upstream simple_spi core doesn't have a slave select register. This is patched locally in orpsoc-cores20:58
olofkIt could be worth checking that the patch applied correctly. You're using de0_nano, right?20:59
Me1234olofk: So to select the EPCS64 I need to write 1 ro b000000420:59
Me1234olofk: Yes, I use de0_nano20:59
olofkI guess so. To be honest, I haven't really looked at simple_spi21:00
olofkTo be sure that the patch applied, could you check in build/de0_nano/src/simple_spi/simple_spi_top.v and make sure that there is a output called ss_o21:00
Me1234olofk: There is ss_o21:03
olofkok, then we can probably rule that out21:04
Me1234My current test program, that does NOT work:Leds show 10100000 and uart outputs the same. http://pastie.org/996707021:06
Me1234olofk: .21:06
olofkMe1234: Make sure to declare the pointers as volatile21:10
olofkIt would be interesting to run that program in a simulator as well21:11
olofkMight want to remove the printf's for that though21:11
olofkDo you have Icarus installed?21:11
olofkand gtkwave21:11
Me1234I think I have, and if I do not I can install it via apt (I use ubuntu)21:12
Me1234olofk: I did not figure out how to run the sim last time I tried it21:12
olofkcool. Then you should be able to run "fusesoc sim --force de0_nano --vcd --elf-load=<path to your elf file> --timeout=<some value. Try 10000 or something to begin with>21:13
Me1234olofk: quite hard using pastie, blocked by provider. Need to connect VPN every time.21:15
olofkThat's annoying21:16
Me1234olofk: Fusesoc ends with error: http://pastie.org/996711021:16
Me1234olofk: it is not verilator21:17
olofkAh crap. I have probably fixed that locally. Recognize the error21:17
Me1234olofk: ERROR: Failed to compile Icarus Simulation model21:17
Me1234olofk : Icarus21:17
olofkThere are some weird syntax errors in the i2c controller.21:18
Me1234olofk: I did not have Icarus installed also. Thought it is verilator21:19
olofkok, this will require some blind hacking. I don't have the right tools on this computer, so I can't test it myself21:21
olofkEdit ~/.cache/fusesoc/i2c/i2c_master_byte_ctrl.v21:21
Me1234olofk: It seems that opencores SVN is down.  Not opencores.org in general, only svn.21:22
Me1234I created a backup copy of ~/.cache/fusesoc, so I have the files21:22
olofkChange "input my_addr" to "input [6:0] my_addr"21:22
olofkThat's good21:22
olofkHopefully that change will be enough to run the simulation21:24
olofk:(21:25
Me1234olofk: connecting VPN caused IRC to disconnect21:25
Me1234olofk: usesoc output now: http://pastie.org/996713821:26
olofkMe1234: God, that must be annoying21:26
olofkAh good. Almost there21:26
olofkI think that your version of libelf is too old21:26
olofkCan't remember if it's called libelf or elfutils in ubuntu21:26
olofkWhich ubuntu version are you using?21:27
Me1234olofk: libelf-dev is not installed21:27
Me123414.0421:27
olofkCould be that easy. Try to install that21:27
olofkAnd you can ignore all the warnings that say "(null):0: tgt-vvp warning: V0.9 may give incorrect results when casting an unsigned value greater than 63 bits to a real value."21:28
olofkThey are harmless icarus warnings, but they are impossible to disable. Very annoying21:28
olofkCan you check the version of libelf in /usr/lib21:29
Me1234Now the results here, after installing libelf-dev: http://pastie.org/996715121:29
olofkPerfect! It works now21:30
olofkSo now you should have a file called build/de0_nano/sim-icarus/testlog.vcd21:30
olofkThis can be viewed with gtkwave21:30
olofkI'm not sure how long simulation time you captured, so you will most likely have to increase --timeout to something larger and rerun the simulation21:31
Me1234olofk: I have it, GTKWAVE shows it.21:31
olofkJust leave gtkwave open and press Ctrl+R to reload the waveform after rerunning simulations21:31
olofkcool. Are you familiar with waveform debugging?21:32
Me1234olofk: No21:32
olofkWell, you've come to the right place to learn :)21:33
olofkIt's probably the most used tool for HDL guys21:33
olofkAnyway..21:33
olofkIn the treeview to the left, navigate down to orpsoc_top/mor1kx/mor1kx_cpu/mor1kx_cpu_cappucino/21:35
olofk(not completely sure about the naming here)21:35
olofkHopefully you will find a signal called traceport_exec_pc_o in the bottom left list21:36
Me1234olofk: Simulation error again :21:37
Me1234Compiling /srv1/srv/o/syn/build/de0_nano/src/elf-loader/elf-loader.c...21:37
Me1234Compiling /srv1/srv/o/syn/build/de0_nano/src/elf-loader/vpi_wrapper.c...21:37
Me1234/usr/bin/iverilog-vpi: 1 file(s) failed to compile.21:37
Me1234ERROR: Failed to build simulation model21:37
Me1234ERROR: Failed to compile VPI library elf-loader21:37
olofkhuh..21:37
olofkBut it worked just before?21:37
olofkSee if you can find any errors in build/de0_nano/sim-icarus/vpi_wrapper.log21:38
olofkhmm.. or elf-loader.log perhaps21:39
Me1234olofk: No such file21:40
olofkhmm21:40
olofkWhat files do you have in that directory?21:41
Me1234olofk: elf-loader.log  icarus.scr  vpi_wrapper.o21:42
Me1234olofk: elf-loader.log contents:21:43
Me1234/srv1/srv/o/syn/build/de0_nano/src/elf-loader/elf-loader.c:26:18: fatal error: gelf.h: No such file or directory21:43
Me1234 #include <gelf.h>21:43
Me1234                  ^21:43
Me1234compilation terminated.21:43
olofkAha. Did you install libelf-dev?21:44
Me1234olofk: Yes, then I installed libelfg0-dev, I think it replaced libelf-dev.21:44
olofkah yes. I remember being confused about which package to use in ubuntu21:46
olofkTry the other one21:46
olofkAnd check if /usr/include/gelf.h exists21:46
Me1234olofk: Sim works again21:46
olofkcool21:47
olofkSo what we're trying to do is to follow the PC and look at the bus accesses to see what's going on21:47
olofkSee if you can locate the PC according to the instructions I pasted some minutes ago21:48
olofkI could probably help out a bit if you send me the vcd file, but it's near bedtime here, so I won't be able to look at it today21:54
olofkGot to go now.22:08
--- Log closed Sat Feb 21 00:00:50 2015

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