| --- Log opened Fri Oct 17 00:00:41 2014 | ||
| -!- FreezingAlt is now known as FreezingCold | 00:30 | |
| ams | juliusb: beer? | 08:18 |
|---|---|---|
| olofk | Anyone here with slightly more SDC/Altera TimeQuest experience than me? | 08:27 |
| _franck__ | olofk: what's your question ? (it doesn't mean I have more expenrience with SDC than you) | 08:47 |
| maxpaln | Hi All, a question from the linux developer: Does the MOR1KX have any ‘hardware assisted TLB reload’? - they handily found this from stekern from July of last year :-) http://lists.opencores.org/pipermail/openrisc/2013-July/001355.html | 08:53 |
| stekern | maxpaln: yes, it does. but the necessary linux patches is still dwelling in a seperate branch | 08:59 |
| stekern | and there's one problem with it that doesn't make it efficient, it's not behind the L1 cache | 09:00 |
| stekern | (and the changes are not the patches in that branch) | 09:02 |
| stekern | it's this: http://git.openrisc.net/cgit.cgi/stefan/linux/log/?h=pte-rework-wip | 09:03 |
| stekern | maxpaln: this was the wb_streamer instantiation I spoke about yesterday btw: https://github.com/skristiansson/orpsoc-cores/blob/multicore/systems/sockit-multicore/rtl/verilog/orpsoc_top.v#L1604 | 09:06 |
| maxpaln | stekern: thanks on both counts - I will pass on the tlb info and have a look myself. I'll browse the wb_streamer implementation a little later when I get some time :-) | 09:07 |
| olofk | _franck__: I had a few questions, but I think I got it sorted out now. | 09:07 |
| juliusb | ams: always | 09:35 |
| ams | juliusb: now? | 09:35 |
| juliusb | ams: it's 6pm somewhere in the world, right? | 09:36 |
| ams | juliusb: exactly!!! | 09:37 |
| ams | the girlfriend isn't convinced by such arguments though ... | 09:39 |
| wallento | 4 is sufficient ;) | 09:42 |
| juliusb | our management certainly thought 4PM was sufficient yesterday, to celebrate being offerred $2.5B for the business | 09:49 |
| juliusb | (or the day before, rather) | 09:50 |
| rah | O_o | 10:27 |
| rah | juliusb: which business? | 10:27 |
| wallento | csr | 10:28 |
| olofk | Alright. Constraining starts to pay off. Added some false path and Fmax is increasing | 10:37 |
| stekern | oh, this is a new fun turn in FPGA development. I have a system that only works when signal tap is enabled and it has timing errors... | 10:50 |
| olofk | stekern: Did you remember to slaughter a lamb with a silver knife while you did Place & Route? | 11:06 |
| stekern | hmm, yes | 11:07 |
| olofk | Then I don't know | 11:10 |
| stekern | wait a second! that wasn't a lamb, it was a wolf! | 11:11 |
| stekern | what was it doing among my lambs, and why was it wearing lamb disguise? | 11:11 |
| olofk | I always put "derive_wolfs [get *lambs*]" in my sdc | 11:12 |
| olofk | stekern: Do you straight away if the CDC from read_done (in sdram_clk) to wb_state.READ (in wb_clk) is a false path? | 11:24 |
| olofk | It doesn't look like it's syncronised with a double FF | 11:26 |
| stekern | "straight away"? | 11:26 |
| olofk | Come on. It's not like it's a hard question ;) | 11:32 |
| hansfbaier | stekern: What would be a good way of starting to understand mor1kx? Where should I start? (maybe the ALU I guess....) | 11:35 |
| stekern | I think it might make sense to follow the pipeline, start from fetch, into decode, into execute (alu), to memstage to writeback | 11:37 |
| stekern | pick a simple instruction to begin with, like an 'l.andi' | 11:38 |
| stekern | olofk: the answer is; nope, I'll stay queer | 11:40 |
| stekern | but you're right, a synchronizer chain is missing there | 11:41 |
| olofk | ah.. I missed some words there :) | 11:42 |
| hansfbaier | stekern: thanks a lot | 12:38 |
| hansfbaier | I'm sorry I can't do very much for openrisc ATM, my health has degraded quite a bit | 12:39 |
| hansfbaier | and I put all my spare time into the saxophone in the moment | 12:39 |
| hansfbaier | that helps me feel healthier | 12:40 |
| hansfbaier | So I work half a day | 12:40 |
| hansfbaier | and practice half a day | 12:40 |
| hansfbaier | more or less | 12:40 |
| hansfbaier | If I am too much in front of the screen that takes a hit on my health | 12:41 |
| olofk | hansfbaier: Sorry to hear that. Hope you will be better | 12:55 |
| hansfbaier | olofk: chronic thing..... seems only to get worse over time ... :[ | 12:56 |
| hansfbaier | BTW I'll be in Germany in December, but orconf is already past isn't it? | 12:56 |
| olofk | hansfbaier: Last weekend. Next year perhaps? We're currently leaning on having it at CERN or in Zürich | 13:00 |
| hansfbaier | Oh, nice | 13:22 |
| hansfbaier | still far away.... | 13:22 |
| hansfbaier | see you... | 13:22 |
| maxpaln | stekern: just noticed your comments about design only working with signal tap enabled. This is nothing new - FPGA engineers have been wrestling with this problem for ages. It's the most tangible version of Schroedingers Cat I have come across :-) | 13:35 |
| maxpaln | glad to see it affects Altera devices too though :-) | 13:36 |
| -!- knz_ is now known as knz | 14:41 | |
| olofk | Oh well. At least I know that the new circuit breaker works now | 15:42 |
| olofk | Turns out that water and electricity isn't always a good combination | 15:43 |
| olofk | Thankfully it only rains a bit over 150 days a year here | 15:44 |
| rschmidlin_ | Are you running some stress tests ony our boards Olof? | 16:01 |
| rschmidlin_ | Btw, which board would you recommend to me? | 16:01 |
| rschmidlin_ | An eval board is what I am looking for. | 16:01 |
| -!- rschmidlin_ is now known as rschmidlin | 16:04 | |
| -!- samus is now known as samus_ | 20:18 | |
| -!- samus_ is now known as samus__ | 20:18 | |
| --- Log closed Sat Oct 18 00:00:42 2014 | ||
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