IRC logs for #openrisc Friday, 2014-08-29

--- Log opened Fri Aug 29 00:00:28 2014
stekernthe "close and comment" and "comment" buttons are all too close to each other03:08
stekernon github03:08
stekernespecially this early in the morning03:08
stekernhesham: can you try the latest commit I just added?09:08
heshamstekern: The revert one?09:08
stekernno, the one after that09:09
heshamSure I will give a try now09:09
stekernthe revert actually failed here too (but it has worked before), only removing one of the constraints made it build on my 14.7 ISE09:09
heshamI hope it works for me, is there any flags I can add to make the building process parallel? like "make -j8" it takes too long09:11
stekernI don't really know what the root issue is, the fails seem pretty random09:11
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heshamstekern: The same problem :/09:31
stekernhesham: for now, the only 'solutions' I can suggest are to either upgrade to 14.7 (that seems to work (by luck)) or just disable the hdmi09:42
heshamstekern: I may have connection  problems with downloading the 14.7 version, I'd leave this solution to the last. How can I disable hdmi?09:43
stekernit seems ISE randomly comes up with routings that's not possible for that signal for some reason, I bet it's possible to solve it in some reasonable way09:43
heshamI just need UART, CPU core, timer, and basic stuff to run RTEMS on09:43
stekern...unfortunately, while I still have my atlys board, it's broken, so I can't do any testing off more elaborate changes :/09:44
heshamI just need to get the .bit file, no need that you run it personally09:45
heshamHow can I disable hdmi?09:45
stekernyes, I can take a look later at trying to fix this more properly (with your help testing the changes)09:46
stekernfirst: https://github.com/openrisc/orpsoc-cores/blob/master/systems/atlys/rtl/verilog/include/orpsoc-defines.v#L1009:46
heshamAnd of the same problem happens, can I use orpsocv2? I tried so but it used some or32-elf-* stuff09:46
stekerncomment that line out09:46
stekernthen comment out everything related to the hdmi in the .ucf09:46
heshamOk09:47
heshamIf some of these trials were successful, I may make a pull request or just tell you what was the commented lines that solved the problem09:48
heshamThanks09:48
olofkstekern: I looked at a few Xilinx answer records yesterday that looked related. They suggested some alternative solutions, but the problem is that their code used an explicit BUFIO2 instance, while it looks like the code in the atlys port just infers one09:54
stekernolofk: how did you come to the conclusion that it's related to BUFIO2?09:59
olofkhttp://www.xilinx.com/support/answers/56113.htm10:05
olofk...and a few others10:05
stekernbut that is another issue, no?10:05
olofkAh ok. I just looked at the description in FuseSoC issue #4510:06
stekernthat was fixed with this commit: https://github.com/openrisc/orpsoc-cores/commit/2dd93fe0ecff025fadb87a5d99dcc9a868b34aef10:06
stekernwhy is that issue even showing as opened on the main issue page?10:07
olofkBecause the comment and close buttons are too close to each other? ;)10:08
stekernah, it *is* opened, the 'closed' only refer to the orpsoc issue10:08
stekerncan you close that?10:08
stekerns/opened/open10:09
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olofkdone10:11
stekernthanks10:29
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stekernnext chapter in my input redirecting endeavour: https://github.com/skristiansson/grabber/blob/master/main.c11:14
stekernto grab the mouse/keyboard on the host while redirecting it to the sockit11:15
stekernit's hard to not click anywhere important on the host otherwise ;)11:20
--- Log closed Fri Aug 29 11:28:30 2014
--- Log opened Fri Aug 29 11:28:44 2014
-!- Irssi: #openrisc: Total of 43 nicks [0 ops, 0 halfops, 0 voices, 43 normal]11:28
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heshamstekern: The HDMI removal solved the problem and I got the .bit file. Next step is to test the design on the board with a bare-metal simple app.11:39
maxpalnHowdy, I am getting curious data width mismatches when trying to use the new wb_intercon system14:34
olofkIs it for the 8-bit slaves?14:35
maxpalnyes14:35
maxpalnI am using the de0_nano board setup as a template - I have copied the wb_intercon.conf file largely as-is apart from removing the unused peripherals14:35
maxpalnbut I get messages like this from the simulator:14:35
maxpalnLength of connection (8) does not match the length of port "wbm_dat_i" (32) on instance "/orpsoc_testbench/dut/i_orpsoc_top/wb_data_resize_uart0"14:35
maxpalnI can see in the wb_intercon.vh file that the signal attached to wbm_dat_i really is defined as an 8-bit signal:14:36
olofkI thought _franck_ had fixed that, but the bug is probably still there. Just change the width of the dat_i/dat_o ports for the 8-bits slaves manually14:36
olofkIn wb_intercon.v and wb_intercon.vh14:36
maxpalnah, ok -14:36
heshamAny hints for how to run openOCD (command line and interface scripts) for to connect to and debug the mor1kx on Atlys board?14:41
olofkhesham: What kind of JTAG interface are you using?14:43
maxpalnolofk: a second question, the orpsoc_top for the de0_nano board instantiates the wb_data_resize() module to resize the 32-bit bus. Is this necessary now? I ask because I am getting port width mismatches on an instantiation of wb_data_resize() from within wb_intercon.14:44
heshamDigilent14:44
olofkmaxpaln: No, that's a leftover from before wb_intercon_gen did that by itself14:44
olofkhesham: I've been using this (from the openocd build dir) ./src/openocd -f ./tcl/interface/altera-usb-blaster.cfg -f ./tcl/board/or1k_generic.cfg -s ./tcl14:46
olofkI think you should use something similar, but replace the altera-usb-blaster-cfg with your adapter14:46
heshamolofk: Thanks I find only one digilent interface, hope it's that one.14:47
maxpalnaha - ok. so I can just connect the 'wb_m2s_<>* signals directly to the peripheral - and they automatically get resized. Graet.14:47
olofkmaxpaln: Are you using the latest orpsoc-cores? I think it was a while since we removed the last wb_data_resize block from the top-level14:48
olofkAnd also, I did some cleanup of the de0_nano port. Nothing major though14:48
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maxpalnok, I think my probl;ems were causd by me including the wb_data_resize in my orpsoc_top.14:54
maxpalnOnce I removed that, I had to back-out the manual changes in wb_intercon and the bus widths now match14:55
olofkah. great14:56
maxpalnThe atlys port would have been a better template :-) It doesn't use the wb_data_resize in my checkout14:56
maxpalnsimulation running - fingers crossed :-)14:57
olofkc00l14:57
olofkWhat sim are you using?14:58
maxpalnjust the or1200-simple at the moment, I'll do something more ambitious once everything is hooked up correctly.14:59
maxpalnor if you wanted to know which SW, I am running Aldec's Riviera14:59
olofkThat was what I wanted to know :)14:59
maxpalnI'm gonna plan to add support for it to fusesoc - it's basically identical to Modelsim with a few switches difference15:00
olofkI want to add support for a crapload of tools in FuseSoC15:00
olofkGreat!15:00
maxpalnIts the best sim I have access to (and probably the most used amongst my customer base) so it makes sense to add it.15:00
olofkI added support for CVC from Tachyon DA a few weeks ago. It wasn't very much work to do that so I suspect you could get riviera going quite quickly15:01
maxpalndarn - x's in my sim, I expected it but the reality always galls.15:02
maxpalnwhoop - that was simpler than I expected! Working simulation :-)15:05
olofkNice to hear. You can soon look forward to those blinking LEDs15:05
olofkhttp://www.eeweb.com/rtz/moment-of-truth15:05
olofkI probably linked to that fifteen times, but I like it because it sums up everything about embedded/digital design :)15:08
heshamolofk: Can I use JTAG programming interface with the cable (USB-MicroUSB) comes with the Atlys board for OpenOCD connection?15:11
olofkhesham: I think so, but not straight away15:13
heshamHere it's http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1 and there is a script called ./tcl/interface/digilent-hs1.cfg15:13
heshamBut I got an error: Error: The specified debug interface was not found (ft2232)15:13
heshamThe run command is: "openocd -f ./tcl/interface/digilent-hs1.cfg -f ./tcl/board/or1k_generic.cfg -s ./tcl"15:14
olofkHas your OS detected the digilent cable?15:14
heshamYou mean enumeration ? djtgcfg enum15:14
heshamDevice: heshamelmatary15:15
hesham    Product Name:   Atlys15:15
hesham    User Name:      heshamelmatary15:15
hesham    Serial Number:  21017850044315:15
heshamI am using it to program the FPGA board (both .bit and .mcs) files15:15
olofkaha15:15
olofkor wait... which cable? The HS-1, or the microusb?15:16
heshamAre not they the same?15:16
olofkThe link you sent was for an external JTAG adapter15:17
heshamNo I mean the USB/ microUSB cable that comes with it15:18
heshamI thought they are the same15:18
heshamit=Atlys board15:18
olofkI think that the microusb port that can be used for programming the FPGA also can be used to connect openocd15:23
maxpalnquick question: my orpsoc-defines.v has a bunch of arbiter  watchdog defines - they were used by the old arbiter. Before I go and remove them I wanted to check that they were really not necessary. I can't find anywhere that they are used but the new arbiter is spread over several files.15:24
olofkBut I would assume that this is connected to the internal JTAG pins in the FPGA, so that you will have to instantiate a xilinx bscan (I think that's what they're called) primitive instead of connecting the JTAG tap to external pins15:24
olofkmaxpaln: No watchdogs in the new arbiter.15:25
maxpalngood - I'll get rid of the defines :-)15:25
olofkShould implement them at some point, but they won't be controlled by `define's when that happens15:25
olofkYou know all those kittens that god killed? That was because people insisted on using a `define instead of a nice and clean parameter15:26
olofkhesham: So for the current atlys system, the easist way would be to hook up an external JTAG adapter (given that you got one) to the pmod port that exposes the JTAG pins15:28
heshamolofk: I would be thankful if you can suggest an external JTAG adapter to buy?15:30
heshamI also found some one asking about the same issue here http://comments.gmane.org/gmane.comp.hardware.openrisc/175915:31
olofkhesham: Sorry. I don't have any since I returned my ORSoC JTAG cable, but I think someone else might know15:31
olofkAnd it might be possible to get the uUSB port working with openocd. We're using that approach on the Altera boards15:32
heshamI will search for a solution for this. Thanks olofk15:32
olofkGood luck. Let me know if you come up with something15:34
olofkIf I get some time I'll try to get it running on my LX9 Microboard. That's probably very similar to the Atlys in this regard15:35
heshamolofk: Would the new feature mentioned here http://openocd.sourceforge.net/ specifically "Xilinx BSCAN_* for OpenRISC support" have something relates to my problem?15:43
olofkhesham: Yes, probably, but there are a few layers here. God, this is hard to explain without a pen and paper :)15:44
heshamI will have to investigate and give it some trials. Hopefully, I will come back again and tell you I found a solution ;)15:45
olofkWe're all hoping for that :)15:45
olofkAnd some of the complication is due to the stupid fucking retarded braindead proprietary JTAG interfaces that the FPGA vendors use15:46
olofkWHY?!?!?!15:46
heshamTo sell out more JTAG Adapter products ?15:47
olofkWell, actally not, since you're using regular USB-microUSB cables15:51
stekernI don't anyone have succeded to run openocd over the digilent interface16:21
stekerns/don16:22
stekern't/don't think16:22
stekernsomeone tried a while ago, but I don't think he got it working16:22
stekernnot sure how hard he tried though16:22
stekernnow when I got my nice grabber, I only need another util to capture the events and merged them into one stream16:25
stekern-d16:25
olofkstekern: Ah ok. I thought that the Digilent hw supported the Xilinx protocol (equivalent to Altera Blaster, can't remember what it's called) as well17:57
olofkI'm thinking of moving orpsoc-cores soon18:07
olofkThe proposed plan looks something like this18:07
olofk1. Clone the repo to a fusesoc-core-lib repo (or something like that)18:08
olofk0. Implement the submodules stuff from blueCmd18:09
olofkNo.. scratch 118:09
olofkHmm.. did I even think this through?18:10
olofkPlan B18:10
olofk1. Keep everything as it is until I have got a good night's rest18:10
olofk4. Profit18:10
olofkAnyway, the idea was to just keep the openrisc-based board ports in the openrisc organization and pull that in as a submodule from a base library18:12
stekernhmm, ok18:17
stekernI'm not sure I understand why you're so eager to move stuff away from the openrisc organization, but it's your baby so it's up to you what you do with it18:19
stekernI mean, even if it's not strictly openrisc specific, it's development is kind of driven by the openrisc community. So it's not entirely out of place under its umbrella I think.18:24
stekernbut... meh18:25
stekern=P18:25
olofkNo, I know. And it's not like it's too much stuff to manage in a single repo18:32
olofkThe reason why I started thinking about it is that I want to add a simple "fusesoc init" that downloads the base repo and writes a default fusesoc.conf to make installations a bit more automated18:33
olofkAnd I thought that once I do that, I want to have the name and location for the base core library set in stone18:33
olofkBut it's not a big deal anyway. Can always change it later on if that should be required18:34
olofkI want to put out a new release before orconf, so if anyone wants a feature for that, now is the time to shout18:36
stekernnot from the top of my head18:44
stekerndoes anyone need anything from 2 broken laser printers, 3 broken ink printers, 1 broken 26" flat screen tv, 2 broken 19" flat screen monitors, 5 broken dvd players, 3 broken vhs players, 2 broken cd players or a *working* 24" crt tv?18:47
stekernmy wife's father recently passed away, and I got the task to go through all the electronics he left, seems he was even worse at throwing stuff away than me...18:48
olofkSorry to hear that18:51
olofkBut you got enough lasers to destroy Alderaan at least18:51
olofkYou can just bring the stuff to orconf, and take back anything that no one wants :)18:53
poke53281stekern: Looks like he had a big cellar. My suggestion would be to throw it away.19:02
stekernI think I'll load it in the car and take it to the recycling station19:03
poke53281He broke a lot of flat screens which is a little bit unusual.19:03
blueCmdstekern: just break out the broken factor and sell what's inside the paraenthesis19:03
stekernhe didn't have a big basement, he was storing all the stuff in his small apartment19:06
olofkI would go office space on the printers if I were you19:06
stekernbut, last I cleaned my "home office" (aka scrap heap) I threw away 2 14" crt tv's, 1 19" crt monitor, 5 broken computer PSUs and 2 digiboxes19:09
stekernit's hard to throw stuff away ;)19:14
stekernyou never know when you might need 5 broken PSUs19:14
olofkYou need them the day after you threw them away. That has always been true, and will always be true19:15
poke532814 years ago I had around 5 meters of magazines. Throw most of it away. Felt better after this. And so far never missed it.19:15
poke53281Ok, I throw them away, after I had everything online or on a DVD.19:16
olofkAs long as no one touches my Sound Blaster 16, I'm ok with throwing stuff away19:17
stekernolofk: yes, but if you wouldn't have thrown them away, you probably wouldn't even have remembered that you had them. that's why it's true ;)19:18
olofkHaha. True :)19:18
stekernsound blaster 16, fancy. I think I still have my first PC sound card somewhere, a sound blaster pro19:19
olofkBut large things have some benefits. I still haven't located my small bag of assorted IC that I lost somewhere in the house around April19:19
olofkWhich would be the preferred linux toolchain right now?20:11
blueCmdhttps://www.efabless.com/ wants to have a chat iwth me20:21
blueCmdapparently very cheap (not sure what that means) ways to get to silicon20:22
olofkThe "Our vision" section looked a bit like the crazy mail that was sent out for the OpenRISC ASIC crowdfunding campaign20:22
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--- Log closed Sat Aug 30 00:00:29 2014

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