| --- Log opened Wed Jun 04 00:00:18 2014 | ||
| -!- stekern_ is now known as stekern | 07:34 | |
| -!- Netsplit *.net <-> *.split quits: rokka, hansfbaier | 08:48 | |
| -!- Netsplit over, joins: hansfbaier | 08:49 | |
| _franck__ | how cool is that: http://pasteboard.co/wZtrI4v.png ? | 09:26 |
|---|---|---|
| _franck__ | jtag serial port is working with openocd | 09:26 |
| _franck__ | it's running under verilator | 09:26 |
| _franck__ | i need to test it on real hardware | 09:26 |
| LoneTech | _franck__: great! :) | 09:40 |
| LoneTech | though I'm not seeing the image | 09:40 |
| _franck__ | :) It's just a log (with colorized text) | 09:41 |
| stekern | sweet! | 09:46 |
| olofk_ | _franck__: Is that the adv_deug_sys uart over JTAG? | 10:42 |
| olofk_ | Hmm.. looks like I managed to outsmart myself when I tried to fix multilib on gentoo. I'm getting "ld: skipping incompatible /usr/lib/libelf.so when searching for -lelf" when I try to run a modelsim simulation | 10:59 |
| olofk_ | wallento: Was this what you experienced on 64 bit machines too? | 11:00 |
| olofk_ | I've tried to comment out -m32 and -melf_i386 but that didn't help | 11:00 |
| olofk_ | whoops.. never mind. | 11:01 |
| olofk_ | I used the system-installed one, so my changes had no effect | 11:01 |
| olofk_ | Anyway... what's the proper way to do this? Do we always want to use 64 bit modelsim on 64 bit machines, and 32 bit on 32 bit machines? | 11:02 |
| olofk_ | Should we autodetect that somehow and set the correct arguments, or de we need runtime switches? | 11:02 |
| olofk_ | Has anyone else seen these errors from the i2c controller with Icarus? http://73a877edbd74da2e.paste.se/ | 11:08 |
| olofk_ | hmm... is the altera modelsim version always 32 bit? I can't find any options to set either 32 or 64 | 11:11 |
| olofk_ | That could explain why I set those flags that wallento commented out even though I'm on a 64 bit machine | 11:12 |
| _franck__ | olofk_: yes it is | 11:22 |
| stekern | maybe the --64bit we've discussed earlier could be applied on that as well | 11:28 |
| stekern | I never got around to update that against your ISE backend | 11:28 |
| stekern | and it should apply to quartus as well | 11:28 |
| olofk_ | _franck__: Cool. That's very helpful especially on the de0 nano since you don't need a dedicated UART-USB adapter anymore | 11:29 |
| olofk_ | stekern: Yes. Patches are welcome :) | 11:29 |
| olofk_ | The modelsim situation looks a bit more shitty though, since we probably need to detect if it's a crippled modelsim (that only supports 32 bit) or a full version | 11:30 |
| stekern | umm, why? | 11:30 |
| stekern | let the user choose with the --64bit command line option | 11:30 |
| LoneTech | don't know how it looks with the altera edition, but my modelsim simply has the 64 bit versions under modeltech/linux_x86_64 | 11:31 |
| LoneTech | also, I think I'd have some trouble using the 32 bit version. I have two sims using 27GB RAM at the moment. | 11:32 |
| olofk_ | LoneTech: Interesting. Haven't looked there | 11:33 |
| LoneTech | the wrapper scripts choose based on MTI_VCO_MODE and uname | 11:34 |
| olofk_ | LoneTech: Just discovered that too :) | 11:34 |
| olofk_ | # On Linux, default to 32 bit unless MTI_VCO_MODE is set | 11:35 |
| LoneTech | not in my version. it picks 64 bit on x86_64 or ia64, if it finds that version of the binary. | 11:36 |
| olofk_ | Hmm.. can't find any 64 bit binaries actually | 11:37 |
| olofk_ | yep. Free version is 32 bit only | 11:38 |
| olofk_ | ok, so I would prefer that FuseSoC did it like this: | 11:39 |
| olofk_ | 1. Set 32/64-bit if user explicitly asked for it. Fail for the free altera version | 11:40 |
| olofk_ | 2. Detect if we run a 32/64 bit system and set modelsim flag + VPI compilation flags | 11:40 |
| olofk_ | Does anyone know if it's possible to use simulation models for Altera primitives in icarus? | 11:46 |
| olofk_ | Xilinx are at least kind enough to proide the verilog for most of the stuff | 11:46 |
| LoneTech | most of it should work fine, iirc | 11:47 |
| LoneTech | found in e.g. altera/12.1sp1/quartus/eda/sim_lib/ | 11:47 |
| ysionneau | Xilinx provies verilog simulation of their IP? | 12:38 |
| ysionneau | provides* | 12:38 |
| ysionneau | working in iverilog? nice! | 12:38 |
| sb0 | yeah, even of the big blocks like CPU cores, if you decrypt them =] | 13:14 |
| olofk_ | LoneTech: Awesome! Thanks! I thought I had scanned the quartus dir, but I missed those | 13:36 |
| LoneTech | in particular 220model.v is actually LPM, which is vendor neutral although only altera seem to care to document their support. I know atmel's support is oddly spotty (it doesn't like 2-input lpm gates) | 13:40 |
| _franck__ | if someone (stekern ?) want to give a try to the jsp, use that repo: https://github.com/fjullien/openOCD/tree/jsp | 14:53 |
| _franck__ | then replace your UART by the JSP | 14:54 |
| _franck__ | like here: https://github.com/fjullien/orpsoc-cores/commit/b09708258140f47ab8c00d576e6c80978c4a7f97 | 14:54 |
| _franck__ | and apply this fix to adv_debug_sys: https://github.com/openrisc/orpsoc-cores/pull/67 | 14:54 |
| olofk_ | From now on it is forbidden to use SDRAM in a design | 19:17 |
| olofk_ | ...at least until I figure out how the hell it works | 19:17 |
| -!- Netsplit *.net <-> *.split quits: kiwichris | 19:24 | |
| -!- Netsplit over, joins: kiwichris | 19:24 | |
| olofk_ | Is the SDRAM on the de0 nano supposed to be running at 200MHz btw? | 19:25 |
| olofk_ | ahh.. oops... | 19:26 |
| olofk_ | It's ok to use SDRAM again | 19:26 |
| sb0 | olofk_, want to try misoc? we have a great sdram controller, which has been ported to the de0nano (iirc) | 19:33 |
| sb0 | :) | 19:34 |
| sb0 | and it supports mor1kx | 19:34 |
| olofk_ | sb0: https://github.com/m-labs/misoc? | 19:35 |
| sb0 | yes | 19:35 |
| sb0 | "make.py -Ot cpu_type or1k" to use or1k instead of lm32 | 19:36 |
| sb0 | on all designs | 19:36 |
| olofk_ | sb0: Cool. Doesn't sound too complicated :) | 19:37 |
| olofk_ | Is the RTL for the SDRAM controller in there, or is it generated by migen on the fly? | 19:37 |
| sb0 | everything is migen-based, except the CPU | 19:38 |
| sb0 | and for now the ethernet controller, but I have a patch for that that I'll merge soon | 19:38 |
| olofk_ | Time to install migen then | 19:39 |
| sb0 | if you insist, you can probably generate rtl for the sdram controller alone and instantiate this in a verilog/vhdl design | 19:39 |
| sb0 | but we have a nice integration lib | 19:39 |
| sb0 | https://github.com/m-labs/misoc/blob/master/targets/mlabs_video.py | 19:40 |
| olofk_ | I am both interested in learning more about migen and getting this damn test bench running... but I think those are two separate issues :) | 19:40 |
| sb0 | e.g. self.lasmixbar.get_master() is all you need to get a new slave port on the sdram arbiter, returns an object that contains the slave signal for those ports | 19:41 |
| sb0 | *this port | 19:41 |
| sb0 | CSR management is pretty good too | 19:42 |
| olofk_ | TIMESPEC "TSise_sucks1" =). (I know the feeling) | 19:44 |
| sb0 | yeah. death to ISE. | 19:48 |
| olofk_ | ucf constraints are the worst thing ever. Especially when you are the only one at your workplace to have a decent understanding of them and is therefore force to write contraints for every damn design ever written at that place | 19:51 |
| olofk_ | What action should I set in make.py? | 19:51 |
| olofk_ | ahh.. tried build-bitstream now | 19:51 |
| sb0 | aw, that sounds awful | 19:53 |
| olofk_ | hmm... git rookie question... how do I get the submodules? | 19:54 |
| sb0 | you can add --recursive to the git clone command... but it's a bit late now | 19:54 |
| olofk_ | ah. got it | 19:54 |
| sb0 | to do it afterwards... I don't remember off the top of my head | 19:55 |
| olofk_ | git submodule init/update | 19:55 |
| olofk_ | sb0: It would actually be interesting to generate verilog from the misoc sdram controller and run some benchmarks on that one compared to wb_sdram_ctrl | 20:05 |
| sb0 | what benchmark exactly? | 20:06 |
| sb0 | performance heavily depends on the access pattern | 20:06 |
| olofk_ | Throughput and latency | 20:06 |
| olofk_ | Yes, that's very true | 20:06 |
| sb0 | the misoc sdram controller with the DDR PHY can achieve 99% throughput (the 1% is for refresh) and 6-cycle latency | 20:08 |
| sb0 | with the right pattern | 20:08 |
| sb0 | most of the latency actually comes from the PHY | 20:09 |
| sb0 | the controller supports page mode, frequency multiplication (generating several SDRAM commands in one system clock cycle), it has a dedicated FSM and request sink per bank, and can precharge/activate one bank while another is being accessed | 20:11 |
| sb0 | it supports read/write grouping to minimize bus turnaround and write recovery time, too | 20:12 |
| olofk_ | That's some cool stuff | 20:12 |
| sb0 | it might be possible to cut some of the latency by optimizing the PHY | 20:12 |
| olofk_ | Can you reuse that for SDRAM/DDR2/DDR3 with just a differnt phy? | 20:13 |
| sb0 | but the PHY uses the Spartan-6 PLLs, SERDES, etc. heavily, which as you might now have more bugs than a rainforest and are a royal pain in the ass to deal with due to various problems with ISE | 20:13 |
| olofk_ | Haven't got a clear view on how those protools differ | 20:13 |
| sb0 | so, if you want to give it a try... patches accepted ;) | 20:13 |
| sb0 | yes | 20:15 |
| olofk_ | I probably spent most of my time in the industry by crawling around in the mud surrounding technology-specific Xilinx primitives. Equipped with some inaccurate data sheets as my only weapon | 20:15 |
| sb0 | actually we already have SDR, DDR2 and LPDDR PHYs | 20:15 |
| sb0 | don't get me started on the s6 io datasheets | 20:16 |
| olofk_ | Virtex-5 and Virtex-6 has been my nemesis | 20:16 |
| sb0 | misoc also gives software access to the PHY | 20:17 |
| olofk_ | meaning..? | 20:17 |
| sb0 | you can bit-bang commands to the SDRAM, and even capture data | 20:17 |
| sb0 | that's very useful for debugging | 20:17 |
| olofk_ | Not quite following.. | 20:17 |
| sb0 | it's also used by the BIOS to send the init sequence | 20:17 |
| olofk_ | ah ok. Now I understand | 20:18 |
| olofk_ | You can bypass the controller, right? | 20:18 |
| sb0 | well, you can set from the software the A/BA pins, and then pulse CAS#, RAS#, etc. | 20:18 |
| sb0 | yes | 20:18 |
| olofk_ | that's cool :) | 20:18 |
| sb0 | and set r/w data for the PHY | 20:18 |
| sb0 | so when you want to debug IO | 20:18 |
| sb0 | you can activate one row in the SDRAM, and use the page buffer like it's SRAM | 20:19 |
| sb0 | this way you put a lot of potential bugs out of the equation | 20:19 |
| olofk_ | I spent about two months hunting down bugs in a stupid Xilinx-provided DDR2 controller. | 20:19 |
| olofk_ | Being able to narrow things down would have helped a lot | 20:19 |
| olofk_ | If I get my hands on a Virtex-6 again, I would definitely like to write a dedicated phy for that and try your controller | 20:21 |
| olofk_ | The one I had used plenty of undocumented primitives with even more undocumented parameters | 20:21 |
| sb0 | had to look at the unisims source? | 20:22 |
| LoneTech | I should continue messing with misoc on atlys | 21:15 |
| LoneTech | sleep first though | 21:17 |
| sb0 | if you have a clean atlys mibuild platform file, please send it :) | 21:39 |
| sb0 | I start to have an accumulation of unmerged patches in my inbox, but I'll get to it eventually... | 21:40 |
| --- Log closed Thu Jun 05 00:00:20 2014 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!
