| --- Log opened Tue Apr 08 00:00:55 2014 | ||
| stekern | Limb: so, do you have an .ucf file, connecting your top module to the outer world? | 03:07 |
|---|---|---|
| stekern | ...ah, missed that link, so yes you do | 03:07 |
| stekern | don't know if it's the answer, but the connection here should be wb_rst instead of wb_rst_i: https://github.com/Limb/orpsoc-cores/blob/nexys4/systems/nexys4/rtl/verilog/orpsoc_top.v#L154 | 03:33 |
| stekern | then there's fun messages like this: http://pastie.org/9002449 | 03:46 |
| stekern | which I don't really understand why it does | 03:46 |
| Limb | stekern: I have a feeling its removing my port connections... but I don't have a clue why | 05:05 |
| Limb | is there any sort of reference on what clock speeds I need to be generating? does it even matter? | 05:07 |
| stekern | no, I don't think so, it seems like it's already throwing everything away at synthesis stage | 05:08 |
| stekern | I'm as confused as you on this | 05:08 |
| stekern | one thing we could try is to connect the sys_clk_pad_i directly to wb_clk, to rule out that it's something in clkgen.v that makes that clock path go away | 05:09 |
| Limb | I've tried a thousand variations | 05:10 |
| Limb | I tried that as well | 05:10 |
| stekern | there's a lot of MACRO stuff going on there, might be that something is spartan6 specific | 05:10 |
| stekern | oh, ok | 05:10 |
| Limb | from what I could find, it seems to be eliminating the connections because it thinks they are null | 05:11 |
| Limb | but I don't see why it is... the connections are valid | 05:11 |
| stekern | yes.. | 05:11 |
| Limb | do I need to include a debug module no matter what? | 05:12 |
| stekern | what if you change the part to spartan6? | 05:12 |
| stekern | (i.e. the same as it was in the atlys board) | 05:12 |
| stekern | well, you should really connect the signals to _something_, but since they will default to 0, I doubt that's an issue | 05:13 |
| Limb | stekern: what's your usual active times? | 05:27 |
| stekern | as in when I'm awake? | 05:27 |
| stekern | usually between 05:30 - 23:00 EEST | 05:31 |
| stekern | changing the part to spartan6 didn't change things | 05:32 |
| Limb | I meant when you were awake yes :) seems between you and olofk, I'm available during your off times he he | 05:36 |
| Limb | I don't have access to my PC right now. I'm hoping I can catch you in ~8 or 9 hours | 05:37 |
| Limb | is it possible I'm not setting a connection on the CPU correctly? I was messing with the clock gen and it seems to be the only thing that actually gets synthesized | 05:39 |
| stekern | as far as I can see, everything is connected as it should... | 05:39 |
| stekern | I did a diff between the atlys orpsoc_top.v and the nexys4.v and everything that matters are connected the same way | 05:40 |
| stekern | I'll swap into my old ISE builder to see if that would make a difference, but that's just a shot in the dark | 05:40 |
| Limb | I was basing my code heavily on the atlys. as far as I can tell in terms of the bare minimum there shouldn't be much of a difference between them | 05:41 |
| Limb | but I tried basing it off the mor1k-generic as well | 05:42 |
| Limb | every idea results in the same blank generation | 05:42 |
| Limb | the most I can get is the clock gen gets implemented that's it | 05:44 |
| stekern | there got to be some small stupid detail we are overseeing | 05:46 |
| Limb | I tried everything I could think of. I don't see why it wants to think nothing exists | 05:52 |
| stekern | yeah, it's crazy... | 05:59 |
| olofk_ | Limb: If you send over your .syr file from the synthesis, I can take a look at that | 06:22 |
| stekern | olofk_: http://oompa.chokladfabriken.org/openrisc/nexys4.srp | 06:26 |
| stekern | that has sys_clk_pad_i and rst_n_pad_i directly connected to wb_clk and wb_rst | 06:32 |
| stekern | oh, and I have hacked your wb_ram a bit, since I don't trust those $clog | 06:39 |
| olofk_ | stekern: I have rewritten most of the stuff in wb_ram. That was just the latest commit that worked :) | 06:41 |
| olofk_ | But yes. I forgot about XST's clog2 problem, so it's probably good to have that rewritten anyway | 06:42 |
| stekern | yeah, I just took away all notion of depth and fed the address width instead | 06:48 |
| stekern | I think that makes more sense for a RAM | 06:48 |
| stekern | and a hint, don't connect stb_i to ack_o ;) | 06:50 |
| stekern | I bet that's just copy-paste from ram_wb | 06:50 |
| olofk_ | stekern: ram_wb ws surprisingly messy when I looked at it. A few naughty latches as well that I have taken care of since | 07:05 |
| stekern | yup, I can't imagine that a cleaned up version would take more than ~20 lines of code | 07:12 |
| stekern | minus port declaration and block ram instantiation | 07:13 |
| stekern | maybe I meant plus in that sentence | 07:24 |
| olofk_ | I'm not getting any wiser with the synthesis stuff. It warns that wb_clk_o, wb_rst_o, async_rst_o and clk100_o has no loads, and I can build the clock generation stand-alone | 07:40 |
| olofk_ | But uart0_stx_pad_o is the only output, so if synthesis determines it's static I guess it could remove everything | 07:42 |
| stekern | it's just strange | 07:47 |
| olofk_ | I think the wishbone spec could need some clarifications | 08:22 |
| olofk_ | Should a burst-compatible slave only register address on the first word and use cti/bte to calculate next address? | 08:23 |
| stekern | ...but as always, all strange things have a natural explanation: https://github.com/Limb/orpsoc-cores/blob/nexys4/systems/nexys4/rtl/verilog/include/uart_defines.v#L135 | 08:27 |
| stekern | register address? | 08:28 |
| stekern | you mean use? | 08:31 |
| stekern | no, all accesses are bound to the incoming address | 08:31 |
| stekern | i.e. it's not like avalon, where you ive a start address | 08:31 |
| stekern | +g | 08:32 |
| olofk_ | (uart) Yes. We should really change that to a parameter and throw away that stupid defines file... or get ourselves a new uart | 08:32 |
| stekern | agreed | 08:34 |
| olofk_ | I started doing some define to parameter conversion, but I realized quite early that it would need quite large changes | 08:35 |
| stekern | so, for your wb_ram, since all accesses are 1-cycle, all you really need to do is: always @(posedge clk) wb_ack_o <= wb_stb_i & wb_cyc_i & !(classic | end_of_burst) | 08:41 |
| stekern | for burst accesses | 08:41 |
| stekern | always @(posedge clk) wb_ack_o <= wb_stb_i & wb_cyc_i & (!(classic | end_of_burst) | !wb_ack_o); | 08:43 |
| stekern | should cover everyting | 08:43 |
| stekern | ..nah, not quite, the end_of_burst will be wrong, but you get the point hopefully | 08:46 |
| olofk_ | Where classic = (wb_cti_i = 3'b000) and end_of_burst = (wb_cti_i = 3'b111)? | 08:46 |
| olofk_ | s/=/== :) | 08:46 |
| stekern | or, no, maybe that's right... you are already acking the end_of_burst when you get wb_cti_ = 3'b111 | 08:47 |
| stekern | hard to write code in IRC ;) | 08:47 |
| stekern | yes, 3'b000 is classic and 3'b111 is end_of_burst | 08:47 |
| stekern | you will of course need to still calculate the next address on bursts, since that's what you are hooking up to the block RAMs address port | 08:49 |
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| --- Log closed Tue Apr 08 10:26:43 2014 | ||
| --- Log opened Tue Apr 08 10:27:02 2014 | ||
| -!- Irssi: #openrisc: Total of 30 nicks [0 ops, 0 halfops, 0 voices, 30 normal] | 10:27 | |
| -!- Irssi: Join to #openrisc was synced in 17 secs | 10:27 | |
| ams | why ... | 10:28 |
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| olofk_ | stekern: wb_ram.v is about 20 lines now as you said | 10:53 |
| olofk_ | http://pastebin.com/jtD7HiCU | 10:55 |
| olofk_ | blueCmd: pastebin because paste.se doesn't have verilog syntax highlighting | 10:56 |
| olofk_ | I need to expand the BFM transactors to generate classic cycles as well. They are quite handy, but they aren't checking everything | 10:57 |
| olofk_ | And to be honest, I don't trust them completely, as I wrote them :) | 10:57 |
| olofk_ | Just stumbled upon f-cpu, the freedom CPU. Can't find any code, but an incredibly ugly homepage :) http://f-cpu.seul.org/f-cpu.org/ | 11:03 |
| stekern | you can get it down to even fewer lines if you remove the excessive empty ones ;) | 11:09 |
| stekern | and 'reg wb_ack_o_r;' | 11:09 |
| stekern | that homepage look all the rage, considering it was made in 2001 | 11:12 |
| -!- dalias_ is now known as dalias | 11:54 | |
| Limb | so it looks like i have a mystery on my hands if you two can't figure out what I've messed up haha | 14:07 |
| Limb | .... you're kidding me | 14:16 |
| Limb | stekern: how on earth did you figure out that uart line would fix it | 14:16 |
| ams | stekern is god. | 14:18 |
| Limb | of course now I get ERROR:MapLib:1209 - Retargeting of PLL clkgen0/pll0 has COMPENSATION attribute | 14:19 |
| Limb | is set to DCM2PLL or PLL2DCM. This is not supported yet in the tools to | 14:19 |
| Limb | target a single MMCM. To enable an unoptimized retargeting please set | 14:19 |
| Limb | XIL_MAP_NO_PLL2MMCM_COMP_ERROR environment variable. | 14:19 |
| Limb | errr sorry for the multi-lines. thought that would paste as one line :X | 14:19 |
| Limb | How do I know exactly what clocks I need to generate? | 14:20 |
| olofk_ | This will have to do http://pastebin.com/ysFzShq3 | 14:28 |
| Limb | olofk: Can I plop that in the previous code you gave me? | 14:29 |
| olofk_ | Limb: The line breaks in Xilinxs log file has annoyed me for many years. Those incompetent idiots just won't fix it | 14:29 |
| olofk_ | Limb: Probably no. You need an extra file as well | 14:29 |
| Limb | I figured hehe | 14:29 |
| Limb | olofk: did you ever implement the xilinx ram method? | 14:30 |
| Limb | Saw you had some code for it | 14:30 |
| olofk_ | http://pastebin.com/16yazM1Z | 14:30 |
| olofk_ | Limb: Yes. The code I just pasted will be implemented as Block RAM (at least on Spartan6) | 14:30 |
| olofk_ | gtg | 14:31 |
| Limb | well I've got a bit file | 14:37 |
| Limb | now I need to figure out how to compile a program and upload it lol | 14:37 |
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| stekern | it was what olofk said about the uart being the only output and a line in the synthesis report complaining about bit 1:0 in the uart addr being unconnected that got me on that track | 15:06 |
| Limb | stekern: you rock :) | 15:11 |
| * Limb has uploaded the bitfile to the board finally \o/ | 15:11 | |
| Limb | but now I haven't a clue what to do lol | 15:11 |
| Limb | hrmmm | 15:25 |
| Limb | Anyone have a guide on how to create a simple program and upload it? | 15:25 |
| stekern | I've used an external jtag adapter and ethernet to upload to the atlys board | 15:29 |
| stekern | it should be possiböe to use the internal jtag tap of the fpga too, and use the existing usb port, but I never tried that | 15:30 |
| Limb | so theres no way to include the program in the bitfile? i'll have to do it manually? | 15:32 |
| stekern | you can of course preload the block ram | 16:07 |
| Limb | stekern: how would i go about doing that exactly? | 16:08 |
| stekern | as olofk have been experimenting, you can use $readmemh to initialize a blockram | 16:12 |
| stekern | thinking this l.lwa/l.swa stuff through a bit right now, I wonder how it would make most sense to indicate that a store conditional have failed | 18:53 |
| stekern | I'm thinking about perhaps set/clear the flag bit in SR | 18:54 |
| stekern | because that would make it easy to conditionally jump right after store conditional | 18:54 |
| stekern | microblaze sets the carry flag | 18:55 |
| stekern | the flag bit is a critical path in mor1kx, so it might be a bad idea to hook up additional logic to that | 19:01 |
| stekern | mips on the other hand set the result in the source register | 19:03 |
| Limb | has anyone used the xilinx virtual JTAG with advanced_debug_sys? | 19:28 |
| stekern | Limb: I think _franck_ mentioned that someone had | 19:47 |
| _franck_ | Limb: yes someone did that with openocd | 20:03 |
| Limb | can't find a thing on how to even access the JTAG output hah | 20:03 |
| _franck_ | you need to instanciate the Xilinx virtual JTAG tap (never used it myself) then connect it to advanced debug interface | 20:06 |
| _franck_ | Limb: look here: http://opencores.org/websvn,filedetails?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2Fverilog%2Fminsoc_top.v | 20:10 |
| _franck_ | look at how the altera vjtag is hooked up here https://github.com/openrisc/orpsoc-cores/blob/master/systems/de1/rtl/verilog/orpsoc_top.v | 20:11 |
| _franck_ | and replace it with minsoc_xilinx_internal_jta from the minsoc project | 20:11 |
| _franck_ | that might work :) | 20:12 |
| blueCmd | stekern: olofk: http://storage.googleapis.com/bluecmd-openrisc/openrisc-x11.png | 21:58 |
| Limb | blueCmd: thats running on a risc? | 22:57 |
| Limb | I can't find a single piece of documentation on this internal jtag thing -_- | 23:28 |
| --- Log closed Wed Apr 09 00:00:57 2014 | ||
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