| --- Log opened Thu Apr 03 00:00:48 2014 | ||
| stekern | olofk: the consequences are that you need to do the verilator tb with systemc | 02:52 |
|---|---|---|
| stekern | it's only used for debug printouts when the caches are turned on in mor1kx, I consider just removing those | 02:53 |
| stekern | hmm... this is interesting, I've found a bug in libgloss crt0.S, but I'm baffled how it haven't been exposed earlier | 03:58 |
| stekern | https://github.com/openrisc/or1k-src/blob/or1k/libgloss/or1k/crt0.S#L258 | 03:58 |
| stekern | _board_mem_base ends up in .bss, but bss is cleared later | 03:58 |
| stekern | so, sp (r1) can obtain random values there | 03:59 |
| stekern | it's easily noticable when running icarus simulations, since _board_mem_base will be x's at line 259 | 04:00 |
| olofk_ | Should we do another teleconf in May? It's halfway between orconf's | 08:22 |
| stekern | sure, why not | 08:25 |
| olofk_ | Any news on the binutils upstreaming? | 08:49 |
| stekern | I think the bureaucracy ball is rolling | 09:04 |
| stekern | I sent away my snail mail monday | 09:04 |
| olofk_ | Has everyone sent their mails? | 09:56 |
| stekern | no idea, it's only me and blueCmd that has mentioned that they've got the e-mail | 09:57 |
| olofk | stekern: So you mean that $time turns into systemC code even though verilator is used with --cc? | 18:22 |
| olofk | stekern: As you've been working on ISE support too, I thought I could show you my IseSection before I push it to see if I should add anything more | 19:12 |
| olofk | Hmm.. how do I edit a commit when I have other commits after that? I tried to checkout an older commit, but apparently this puts me in 'detached HEAD' state which sounds extremely frightening | 19:16 |
| olofk | Ha! I made it with git rebase --interactive | 19:20 |
| olofk | git is fun! | 19:20 |
| olofk | _franck__: simulator.py can't find fusesoc.verilog after I applied your patches. Did I miss something? | 20:40 |
| olofk | hm... there are more changes that need to be done in simulator.py | 20:42 |
| olofk | We really should start working on the regression test suite :/ | 20:43 |
| olofk | Think I got it fixed now, but there's a warning when I run fusesoc | 21:02 |
| olofk | Quick hack --> http://pastie.org/private/xckizbatayqtk83jplutga | 21:03 |
| olofk | A better solution would avoid exposing VerilogSection in simulator.py | 21:04 |
| --- Log closed Fri Apr 04 00:00:50 2014 | ||
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