| --- Log opened Thu Mar 13 00:00:18 2014 | ||
| blueCmd | man, I this is weird. I got this to work sort of once. I have the SOF covered, that works - I can cold boot it and start openocd (although I need to start OpenOCD twice, the first time it is never able to connect after a cold boot) | 00:38 |
|---|---|---|
| blueCmd | mdw 0x100 does _not_ read my vmlinux image. i got it to do that without using load_image once, but I'm not able to reproduce that | 00:38 |
| blueCmd | currently mdw 0x0 and mdw 0x0 reads 0ff00ff0 which seems like some sort of init value for the ram. | 00:39 |
| blueCmd | I looked at http://oompa.chokladfabriken.org/tmp/orpsoc.cof and used relative address 0 (since I the ihex I have seems to map perfectly fine starting at 0x0 and the CPU should jump to 0x100 when the boot rom is executed) | 00:41 |
| blueCmd | stekern: olofk: any relevant ideas regarding how to debug this would be helpful | 00:42 |
| blueCmd | now, sleep. | 00:42 |
| stekern | blueCmd: what do you mean by "i got it to do that without using load_image once, but I'm not able to reproduce that"? | 03:50 |
| stekern | are you trying to cold boot the board with orpsoc and a vmlinux in the flash? | 03:53 |
| stekern | it wasn't really clear from your decription what you are trying to do when it doesn't work ;) | 03:54 |
| stekern | if so, the bootrom need to read the vmlinux image from the flash in order for that to work | 03:57 |
| stekern | into the RAM that is | 03:57 |
| stekern | I don't think the infrastructure to build a rom like that is available in orpsoc-cores, but you can easily steal the .S for it from orpsocv2 | 03:58 |
| blueCmd | stekern: i see. so my thought was that the FPGA, while reading the SOF would simply do a JTAG write of the rest of the contents | 08:35 |
| blueCmd | stekern: "are you trying to cold boot the board with orpsoc and a vmlinux in the flash?" yes | 08:36 |
| blueCmd | sorry for being uncomprehensive - i tend to be that when I have hours of thoughts to dump | 08:36 |
| blueCmd | stekern: so basically I need a boot rom that reads the flash and writes the SDRAM? | 08:42 |
| blueCmd | and the reason I got it to work once was probably because of luck and the RAM just kept it's state. that explains why it booted and crashed halfway though the boot | 08:42 |
| olofk | A boot rom generator would be a nice addition to orpsoc-cores | 08:44 |
| olofk | It's been on my TODO list for quite a while | 08:45 |
| blueCmd | olofk: it won't be much longer | 08:50 |
| blueCmd | stekern: ah, looking at the orpsocv2 code a lot of things feel into place in my head, thanks | 08:58 |
| stekern | blueCmd: yup, seems you've got the picture clear, and I was thinking the same, your one-time working scenario was probably because of RAM still containing old data | 09:01 |
| blueCmd | stekern: fun thing, I actually wrote a boot rom a while back. (http://blog.cmd.nu/2012/01/bootloader-for-de-2-board-with-openrisc.html) - simpler but the same concept :) | 09:06 |
| blueCmd | I guess I put too much faith in the Flash loader in the fpga | 09:08 |
| olofk | Just done some spring cleaning. Only four exit(1) left in the fusesoc module. Feels good | 09:31 |
| olofk | It would be cool if someone would do a GUI around fusesoc. Don't know what it should do, but it's fun to click at things | 09:32 |
| olofk | _franck_: Does the resize function in wb_intercon_gen work? It looks like the slave port is still 32 bits | 10:00 |
| _franck_web_ | it doesn't generate port in the rigth size. However those ports are 8 bits, bits [32..8] are not connected | 10:04 |
| _franck_web_ | *[31..8] | 10:04 |
| olofk | ah ok | 10:04 |
| _franck_web_ | should be fix (but I think it wasn't trivial so I left it for someone else :)) | 10:05 |
| olofk | No, the code in wb_intercon_gen is surprisingly messy. I'll just change the port size manually for now | 10:05 |
| _franck_web_ | what do you mean by "No" ? You meant don't fix it but rewrite it completely ? | 10:09 |
| olofk | Forget that "No". It was just a typo | 10:10 |
| _franck_web_ | ok | 10:11 |
| olofk | But next time we want to add a feature to wb_intercon_gen, we might have to rewrite it. But I guess that's up to whoever changes it next time | 10:11 |
| _franck_web_ | That's a mess, I agree | 10:13 |
| _franck_web_ | May be I'll do it since I would like to practice my Python skills | 10:13 |
| stekern | vhdls restriction that you can't read an output port is as stupid as verilog making a distinction between reg and wire. | 10:52 |
| olofk | Yes. Those languages are equally fucked up, but in different ways | 11:38 |
| stekern | mmm, you could make a perfect or a really screwed up solution by combining them | 12:06 |
| stekern | perfect is perhaps stretching it, but... | 12:06 |
| olofk | :) | 15:18 |
| olofk | stekern: BTW, the VHDL limitation is removed in vhdl2008 | 16:21 |
| olofk | ie. You can read outputs | 16:21 |
| stekern | that's nice, a lot of the really stupid things in vhdl is solved in that | 16:30 |
| stekern | maybe I should just secretly switch all projects at work to use that | 16:35 |
| blueCmd | http://storage.googleapis.com/bluecmd/buildserver.jpg - openrisc debian build server | 22:59 |
| poke53281 | Great | 23:13 |
| poke53281 | What FPGAs do you use? | 23:13 |
| poke53281 | You should eat the banana. Does not look good anymore;) | 23:13 |
| --- Log closed Fri Mar 14 00:00:19 2014 | ||
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