| --- Log opened Fri Jan 31 00:00:18 2014 | ||
| jonibo | happy new year, omoc! | 08:28 |
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| jonibo | hmmm... not around, I see... oh well, he'll get it in the logs! :) | 08:29 |
| --- Log closed Fri Jan 31 10:11:03 2014 | ||
| --- Log opened Fri Jan 31 10:11:20 2014 | ||
| -!- Irssi: #openrisc: Total of 33 nicks [0 ops, 0 halfops, 0 voices, 33 normal] | 10:11 | |
| -!- Irssi: Join to #openrisc was synced in 17 secs | 10:11 | |
| jungma | Hey, is there any CA SystemC or AT TLM2 model available of OR? | 10:45 |
| olofk_ | jungma: Not really, but you can generate a systemC model of the RTL code with verilator | 10:48 |
| jungma | olofk_: verilator is something like carbonizer? | 10:50 |
| olofk_ | Haven't heard of carbonizer. Do you have a link? | 10:59 |
| olofk_ | verilator generates cycle-accurate c++ or sysC code from synthesizable verilog. We use it quite a lot for OpenRISC verifcation as it's blazing fast compared to event-driven sims | 10:59 |
| olofk_ | http://www.veripool.org/wiki/verilator | 10:59 |
| ams | olofk_: nice | 11:13 |
| ams | olofk_: anything particular to watch out for? | 11:13 |
| jungma | olofk_: http://www.carbondesignsystems.com/virtual-prototype-model-creation/ | 11:17 |
| jungma | olofk_: that sounds good, it might be reasonable to use an OpenRISC CA core for my investigations. Are there some documents? How to create the core and how to transform it into SystemC? | 11:20 |
| olofk_ | ams: Nothing that comes to mind | 11:37 |
| ams | olofk_: i am just cautious ... i suppose, found a nice little place in paris for not to much ... | 11:38 |
| olofk_ | jungma: No specific documentation, but you can run the workflow in our SoC simulation framework (orpsocv3) and let that generate the model for you | 11:40 |
| olofk_ | jeremybennett might have written an app note specifically for OpenRISC, and the verilator page has information on general usage | 11:41 |
| jungma | olofk_: i only need the core, without any peripherals, i'll have a look, thanks for the information | 12:11 |
| jungma | olofk_: yeah, i was able to convert the core and import it to synopsys' platform architect ;) | 15:13 |
| olofk_ | jungma: Awesome. That's good to know | 15:29 |
| olofk_ | With verilator? | 15:30 |
| jungma | olofk_: yes, but it is doing nothing, first i have to write WB to TLM transactors ;) | 16:30 |
| --- Log closed Sat Feb 01 00:00:19 2014 | ||
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