| --- Log opened Thu Nov 21 00:00:34 2013 | ||
| hikenboot | poke53281, when i ran make newlib_toolchain...it ran through after a second time (missing a couple of files) and it completes however it does generate the following "install-info: No such file or directory for /opt/or1k/share/info/libquadmath.info is this something to worry about? | 02:08 |
|---|---|---|
| poke53281 | I think you can ignore the error. | 02:11 |
| poke53281 | I have removed the doc from the installation. | 02:15 |
| hansfbaier | stekern, juliusb: http://pastie.org/8497264 | 04:14 |
| stekern | hansfbaier: do you have the systemc headers/libraries installed and in "path" | 05:24 |
| stekern | with "path" I mean SYSTEMC environment variable set | 05:25 |
| stekern | as for the libor1ktrace, that looks familiar, but I can't remember how/if I got that solved | 05:26 |
| hansfbaier | stekern: Which version of systemc should I download? From Accerlera direct, or the github? | 08:18 |
| stekern | hansfbaier: to be honest, I'm not sure, I installed mine probably 3 years ago or something like that | 08:55 |
| hansfbaier | stekern: I tried 2.3, but got compile errors, now I try 2.2 | 08:55 |
| hansfbaier | stekern: trying to install systemc is an exercise in frustration | 09:52 |
| stekern | hansfbaier: I know :( | 09:55 |
| stekern | that's why my installation is three years old... | 09:55 |
| hansfbaier | stekern: $ find /usr/local/systemc-2.2/ -name systemc | 09:58 |
| hansfbaier | /usr/local/systemc-2.2/include/systemc | 09:58 |
| hansfbaier | no executable named 'systemc' there. | 09:58 |
| hansfbaier | weird | 09:58 |
| hansfbaier | ah it's a header | 10:00 |
| stekern | yes | 10:00 |
| kamy | hi everyone | 14:59 |
| kamy | I have a question regarding orpsoc (v2 or v3) | 15:00 |
| kamy | are there any scripts or other automation mechanisms to generate a top level module (something like orpsoc_top.v) from the modules specified in a configuration | 15:02 |
| stekern | kamy: no, but it's on the wishlist | 15:03 |
| kamy | stekern: thanks! Would you happen to know of any docs or guidelines that could help me create an SoC from scratch? I'm thinking about a multicore SoC consisting of configurable mor1kx cores and memory components. | 15:12 |
| stekern | the de0_nano or de1 ports should be pretty good starting points: https://github.com/openrisc/orpsoc-cores/tree/master/systems | 15:14 |
| flozn | hi, i have an issue with the synthesis of my minsoc system at spartan 6. since i use a second clock domain, the cpu/wishbone changes *alot* (planahead analysis) with every small code change. putting the second clock domain in a area group and define cross clk TIG's does not help. how can i improve the synthesis of the wishbone clk domain? does someone knows this case? thanks alot! | 15:43 |
| flozn | hm, noone? ... let's give the forum a try... | 15:55 |
| stekern | flozn: you have to be more patient, people aren't just sitting around waiting to answer your questions | 16:00 |
| flozn | ah, ok. thanks! i will wait! | 16:02 |
| flozn | if someone is interested in solving strange problems, here the details of mine ;) : http://opencores.org/forum,OpenRISC,0,5351 | 16:26 |
| stekern | flozn: first, why do you want to split the clocks? | 16:50 |
| stekern | reading from the forum post, it should be fine to run the whole system off the 50 MHz clock | 16:52 |
| stekern | and what selftest are you speaking about? the adv_debug_sys selftest? | 16:55 |
| stekern | also, mind that there's another CDC between the adv_debug_sys jtag clock and the wishbone clock and the cpu clock | 17:02 |
| flozn | thanks for answering! yes, the adv_debug_sys test. but nevertheless, the system runs into errors when using gdb | 17:03 |
| stekern | yes, but that's still within the adv_debug_sys domain... | 17:03 |
| flozn | hm, maybe i have to add some constraints to the jtag clock domain? | 17:03 |
| stekern | I would try that | 17:04 |
| flozn | first, why do you want to split the clocks? the pll i need does not work with the 25mhz system clock. | 17:04 |
| stekern | ? | 17:04 |
| stekern | why does the system clock have to be 25 MHz? | 17:05 |
| flozn | i need two clocks (x1, x7) for lvds. if the pll is sourced by 25mhz, the vco range is not met. | 17:05 |
| flozn | more than 25mhz i did not get sucessfully synthesized (somewhat between 45 and 50mhz is maximum frequency of cpu at xst) | 17:06 |
| stekern | I had or1200 running at 50MHz on the atlys board without problems... | 17:07 |
| flozn | ok, if you say! than i will try to run it also at 50mhz. maybe the cross clock problem get solved by this. | 17:08 |
| flozn | do you had to make some improvement? flags, or1200-defines or other changes? | 17:09 |
| stekern | but anyway, for the first problem, that should just be a matter of adjusting the multiplier and divider so vco matches | 17:09 |
| flozn | as far as i know, there was no way to get this working. either the 400mhz minimal vco frequency was not met (to low) or the minimal output frequency (after divider?) with 19mhz was not reached (to high). | 17:10 |
| flozn | does the adv_debug_sys selftest finish without problems on a sucessfully build soc? | 17:11 |
| stekern | I never used adv_debug_sys with the atlys board | 17:12 |
| flozn | hm ok. how do you copy the software to sram? | 17:12 |
| stekern | there's two answers to that question: 1) use a bootrom that copies a bootloader into SDRAM from flash and then load over ethernet (or read from flash) 2) use another debug system | 17:14 |
| stekern | I used the mohor debug system for the orpsocv2 atlys board port | 17:15 |
| flozn | and this is included in your sucessfully build 50mhz soc? | 17:15 |
| stekern | yes | 17:15 |
| flozn | may i give your solution a try! | 17:15 |
| stekern | http://git.openrisc.net/cgit.cgi/stefan/orpsoc/ | 17:16 |
| flozn | thanks! the last time i tried to build orpsocv2 for atlys out of the box, it doesnt work. there were timing violations as i remember ... but if you run it on altys i am looking forward! | 17:18 |
| flozn | nevertheless it is a strange behaviour of the minsoc system :( | 17:19 |
| stekern | I've had the ethmac acting up and giving timing violations, but not on the cpu at 50MHz | 17:21 |
| flozn | but with a higher frequency? or lower? | 17:23 |
| stekern | I meant, there haven't been timing violations on paths inside the cpu at 50MHz | 17:23 |
| flozn | ah! ok! with the minsoc dev version there are no violations at 25mhz (only the 1.0 version had violations) ... and this is the strange fact! why does map/par say everything is fine (even no hold score at first par stage), and the system fails :/ | 17:25 |
| stekern | are you sure the system fails, and not just the connection between adv_debug_sys and the system? | 17:26 |
| flozn | well, not 100% sure | 17:27 |
| stekern | because all the problems you have described have had relations to the adv_debug_sys | 17:27 |
| flozn | the adv_debug_sys behaviour strongly changes with small changes in the code and constraints (e.g. area group) . the cases are: CRC error (totally crashed), SRAM error and CPU error. in the last case gdb connects but the cpu halts or throws errors | 17:28 |
| stekern | but, besides, TIG doesn't magically solve problems, you have to have proper CDC between the signals *before* you add the TIG. But from your description in the forum, it sounds like you have that handled | 17:28 |
| flozn | do you mean synchronize blocks? yes they are included. | 17:29 |
| stekern | yeah, I don't know, I've had problems with the adv_debug_bridge throwing CRC errors (on different boards) but using the same system with openocd have worked fine | 17:29 |
| stekern | we never got to the bottom of that... | 17:30 |
| stekern | iirc | 17:30 |
| flozn | hm, openocd i also have available. this i will try too. good tip! | 17:30 |
| flozn | as you described, the adv debug sys seems to be pretty buggy?! | 17:31 |
| stekern | but I'd look closely at the CDC between the signals from adv_debug_sys and cpu/wb | 17:32 |
| stekern | how are you connecting to it? with an external jtag debugger? | 17:33 |
| flozn | at the moment i don't know much about the CDC of adv_debug_sys and cpu/wb | 17:33 |
| flozn | jip, ftdi2232 | 17:33 |
| stekern | ok, I guess that should be fine... and I think adv_debug_sys is less buggy than the alternative... | 17:34 |
| stekern | that | 17:34 |
| stekern | 's why I suggest you should take a look at it, it might be so that the problems we saw was related to that too | 17:34 |
| flozn | ok! | 17:35 |
| stekern | but the test with openocd is probably wise too, I haven't had any problems with the adv_debug_sys + openocd combo | 17:35 |
| flozn | fine :) ! | 17:36 |
| flozn | may i ask some private question? ;) are you a professional with fpga? or is it just hobby? ... after all this struggle with minsoc i asked myself how such a complex fpga system is verified for industrial use?! | 17:38 |
| stekern | I do some fpga work at work, but my job title is "sw designer" | 17:39 |
| stekern | but nothing what I do at work is related to openrisc | 17:39 |
| flozn | ah ok. nevertheless, do you know about some kind of layout vs schematic for xilinx fpga? | 17:42 |
| stekern | layout vs schematic? | 17:44 |
| flozn | i mean some kind of verification for the synthesized hardware - whether it matches the describing netlists. (not just try the final product at the fpga) | 17:46 |
| stekern | you can rrun post synthesis simulations | 17:47 |
| flozn | do such simulations show problems like the adv_debug_sys CDC issue? | 17:48 |
| flozn | (i answer myself: the testbenches for my synchronizer blocks show the right behaviour. but i think the adv_debug_sys sync logic is also correctly described. so the simulation will not show errors which could be avoided due to CDC constraints. not?) | 17:56 |
| flozn | finally, thanks *alot* for all your help!!! now i'm optimistic :) ! | 18:00 |
| olofk | Did anyone else go for a parallella board via the kickstarter? | 20:05 |
| --- Log closed Fri Nov 22 00:00:35 2013 | ||
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