| --- Log opened Fri Nov 01 00:00:05 2013 | ||
| stekern | _franck_: it usually does :( | 04:11 |
|---|---|---|
| olofk_ | I gave Xilinx and Altera some reprimands for their proprietary debug interfaces on twitter. I'm sure they will stop now after I have told them it's bad! | 07:37 |
| stekern | I would be very surprised if they wouldn't take notice when a member of such a high profile project as openrisc raise their voice of opinion! | 07:57 |
| olofk_ | I'm waiting for flowers and a written apology | 08:16 |
| olofk_ | Have you heard about the new Stratix 10 btw? It will have a quad core 64 bit ARM. That's pretty insane | 08:17 |
| stekern | I'm not following the high-end fpgas so much | 08:21 |
| -!- rmarko is now known as impure_hate | 08:33 | |
| -!- Netsplit *.net <-> *.split quits: mick_laptop | 08:58 | |
| rah | what speed do the FPGA chips run at in the SoCKit? | 09:04 |
| rah | according to the "Clock Tree Performance for Cyclone V Device" table in the datasheet, the "Global clock and Regional clock" is 460MHz | 09:04 |
| rah | which seems quite good | 09:04 |
| stekern | rah: the question is flawed, so it's hard to answer it | 09:05 |
| stekern | there is only one fpga chip on the sockit board | 09:06 |
| rah | stekern: how is the question flawed? is the clock speed variable? | 09:06 |
| stekern | and you can clock different cores at different speed inside the fpga | 09:06 |
| rah | s/in the SoCKit/in the SoCKit boards/ | 09:06 |
| rah | I see | 09:07 |
| stekern | and it depends on the core design (and the FPGA) how fast you can clock it | 09:07 |
| rah | what effects the clock speed in the core design? | 09:08 |
| stekern | so, to be able to answer your question, you need to have a specific core in mind | 09:08 |
| stekern | how long combinatorial paths you have (basically) | 09:09 |
| rah | ok | 09:10 |
| rah | this is going above my head now | 09:10 |
| rah | what kind of clock speeds can you get with an openrisc core? | 09:10 |
| -!- mick_lap2op is now known as mick_laptop | 09:38 | |
| stekern | rah: I haven't pushed it on the sockit, but around 90 MHz without mmu and 75 Mhz with on de0 nano | 09:59 |
| olofk_ | Stupid webchat. I thought it was unusally quiet on the channel. Seems I was disconnected | 10:03 |
| rah | stekern: that's quite low :-/ | 10:59 |
| stekern | rah: there's room for improvement, but no, it's not very low | 11:19 |
| stekern | I think NiosII, that is optimised for altera can go up to around 150 MHz | 11:22 |
| stekern | on that fpga | 11:23 |
| stekern | and that soc | 11:25 |
| olofk_ | I got a MicroBlaze running at 125MHz. Could probably clock it a bit higher, but not much | 11:42 |
| olofk_ | stekern: Do you have a feel for the IPC for Nios and MicroBlaze? | 11:43 |
| rah | stekern: I'm comparing it to desktop CPUs | 11:45 |
| rah | olofk_: how do you determine whether a clock speed is too high? | 11:47 |
| rah | what does "too high" mean? :-) | 11:48 |
| rah | is it a heat issue? | 11:49 |
| rah | (like with desktop CPUs?) | 11:49 |
| olofk_ | rah: It's usually not a heat problem. The electrical signals don't have time to reach the next register is the clock is too fast | 11:52 |
| olofk_ | But that's the same thing about desktop CPUs. Even if you could cool them, they wouldn't be able to go infinitely fast | 11:53 |
| rah | olofk_: I see | 11:54 |
| stekern | olofk_: I think we are up to par with both of them in mor1kx cappuccino | 11:54 |
| stekern | we beat the coremark/mhz scores for the microblaze results that are published at least, but they were done with a quite old gcc | 11:55 |
| stekern | rah: yeah, it's a well known fact that FPGAs are not very fast, especially not the lowend ones | 12:05 |
| LoneTech | olofk_: that can be a heat problem. higher heat means higher resistance which makes the effective RC filter of signal wire into MOSFET gate slower | 12:12 |
| LoneTech | this is why overclocking gets easier as you chill things a lot | 12:12 |
| olofk_ | I'm off | 12:26 |
| rah | stekern: why kind of speeds could you get with a higher-end FPGA? | 13:13 |
| rah | stekern: I looked at the datasheet for the top-end Stratix V chip, and they quote 717MHz compared to 460MHz in the Cyclone V | 13:15 |
| rah | stekern: would you expect to get an increase in the speed of a processor core, proportional (or thereabouts) to these quoted speeds? | 13:17 |
| _franck_ | it's ready: https://github.com/fjullien/openOCD | 17:00 |
| _franck_ | please use branch usbblaster2 | 17:01 |
| _franck_ | ./configure --enable-usb_blaster_2 --enable-usb_blaster-libftdi --enable-maintainer-mode | 17:01 |
| _franck_ | sudo ./src/openocd -f ./tcl/interface/altera-usb-blaster.cfg -f ./tcl/board/or1k_sockit.cfg -s ./tcl | 17:01 |
| _franck_ | and tell me if it works for you.... | 17:01 |
| --- Log closed Sat Nov 02 00:00:06 2013 | ||
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