| --- Log opened Mon Sep 23 00:00:08 2013 | ||
| -!- Netsplit *.net <-> *.split quits: stekern, mick_laptop | 00:24 | |
| -!- Netsplit over, joins: stekern | 00:28 | |
| * stekern is happy that git style patches work with orpsoc's patch system | 04:54 | |
| stekern | now if only the cache would be a bit smarter ;) | 04:55 |
|---|---|---|
| stekern | haha, I just noticed the "timing constraint" geekness on this page: http://opencores.org/or1k/OpenRISC_Project_Meeting#Schedule | 04:57 |
| olofk | stekern: Yes, the cache mechanism isn't all that clever | 05:19 |
| olofk | Many things to implement. Little time to do it :( | 05:21 |
| stekern | word bro | 05:22 |
| olofk | stekern, _franck_ : Now that you have used orpsocv3 a bit. Are there any specific tasks that is missing from ORPSoCv2? It would be great to be on feature parity quite soon | 05:22 |
| stekern | it's not that bad when you are aware of it, but it's a bit surprising that when you do changes to .core files or add patches, they don't propagate automatically to your build directory if you don't wipe the cache | 05:23 |
| stekern | I'm missing the "test-suite", but I think that should be brought in as a seperate project | 05:24 |
| olofk | Yeah, I think so too. I have precompiled binaries of the orpsocv2 or1200 tests in another directory that I run regularly | 05:26 |
| stekern | we should probably take the tests from mor1kx-dev-env though | 05:28 |
| olofk | Are they improved versions of the same tests, or additional ones? | 05:29 |
| stekern | both | 05:29 |
| olofk | Great. I have found some oddities in the tests in orpsocv2 | 05:29 |
| olofk | Talking about mor1kx-dev-env, have you considered moving/copying mor1kx-monitor to the mor1kx repo? | 05:30 |
| stekern | ah, yeah, that... didn't juliusb_ say he was ok with that? | 05:34 |
| olofk | Probably. Can't remember | 05:40 |
| stekern | I think he did, so I'll just copy it over there and then he can scream at me if he don't like it ;) | 05:42 |
| olofk | Great. Then I can drop mor1kx-dev-env from orpsoc-cores I guess. Or could it still be useful to have it as an orpsoc core? | 05:44 |
| stekern | at least not if we break out the tests from it | 05:47 |
| stekern | I want to run the tests on the sockit too | 05:50 |
| stekern | so breaking them out would be beneficial for that too | 05:51 |
| stekern | I'm working on a or1k-elf-loader for that right now, so should be easy to adapt | 05:52 |
| stekern | the only thing missing is how to get the l.nop reports | 05:52 |
| stekern | I mean, I'm working on a or1k-elf-loader for sockit | 05:56 |
| olofk | And I got one for wb_sdram_ctrl in the works for de0 and friends | 06:01 |
| stekern | great | 06:03 |
| stekern | I meant an or1k-elf-loader on the real hw | 06:03 |
| olofk | Ahhh.. right | 06:04 |
| olofk | That's like 37 times cooler | 06:04 |
| olofk | More or less | 06:04 |
| stekern | =) | 06:05 |
| stekern | I think it's 37.2326 | 06:05 |
| olofk | Yeah, you could be right. I did the calculations on my P90 | 06:06 |
| stekern | huh, on this? http://en.wikipedia.org/wiki/FN_P90 | 06:08 |
| olofk | I was referring to something else, but I guess they can be equally dangerous in the wrong hands :) | 06:10 |
| olofk | Stupid TLA | 06:11 |
| stekern | sso this then? http://en.wikipedia.org/wiki/P90X | 06:11 |
| olofk | Yes! That's the one | 06:13 |
| stekern | Ok, then I'm with you. I agree that to do a full body workout, you can't leave out the brain gymnastics | 06:15 |
| olofk | lol | 06:18 |
| Powermaniac | So if you don't mind me asking, how did you guys learn to do this? | 06:19 |
| olofk | Powermaniac: It came to me in a dream | 06:19 |
| stekern | we do a lot of training on our p90x's | 06:19 |
| Powermaniac | xD | 06:19 |
| Powermaniac | I'm going to assume you did university degrees to learn how to do this. | 06:21 |
| Powermaniac | ...right? | 06:21 |
| stekern | I have an EE degree, but to be honest, most is self-learnt | 06:21 |
| stekern | but I'm not going to deny that it was the univerity that introduced me to digital design | 06:22 |
| olofk | Same here | 06:23 |
| Powermaniac | Okay. Hmm, was going to ask then if there are any books/sites/etc. you recommend? | 06:23 |
| Powermaniac | Wait make that I am still going to ask* | 06:24 |
| ams | "do this"? | 06:24 |
| Powermaniac | ams: Work on ORPSoC, and OpenRISC1200 | 06:24 |
| ams | I will speak for stekern and olofk: Cause it is fucking fun. | 06:25 |
| olofk | I only do it to get laid | 06:26 |
| Powermaniac | ... | 06:26 |
| Powermaniac | olofk: And how is that working out for you...? | 06:26 |
| ams | i'm just a groupie ... | 06:26 |
| Powermaniac | Hahaa | 06:26 |
| stekern | Powermaniac: I think I've only read one book on digital design, and that was the book we were assigned in university | 06:27 |
| stekern | I'm more of a learn-by-doing kind of guy | 06:27 |
| ams | Spending a helluva time doing stuff is the key ... | 06:28 |
| Powermaniac | stekern: But how do you know what you are even doing...? | 06:28 |
| olofk | I learned the ancient arts of OpenRISC from a scroll in the temple in Tibet where I was meditating about bus interconnects | 06:28 |
| stekern | for reference, this was the book: http://www.bokus.com/bok/9789144024714/vhdl-for-konstruktion/ | 06:29 |
| stekern | you get the bonus task of learning swedish to read it ;) | 06:29 |
| Powermaniac | Also so do both of you (olofk and stekern) use the DE0 Nano board? And if so besides developing ORPSoC do you have any other uses for it? Like what do you connect it to (Stekern I know your answer to this part). | 06:29 |
| Powermaniac | stekern: Aren't you from Finland though, I thought you would know Finnish not Swedish? (Not very knowledgeable on European countries). | 06:30 |
| olofk | Powermaniac: I haven't actually used my FPGA boards for anything more than demonstrational purposes at conferences. | 06:30 |
| olofk | I've been having lots of ideas, but never had time to do anything with them | 06:31 |
| Powermaniac | olofk: What do you hope to achieve with the ORPSoC then? Where do you see yourself going with it? | 06:31 |
| stekern | Powermaniac: I'm from Sweden, but I currently live in Finland. I know Finnish, but Swedish is my mother tongue. | 06:32 |
| Powermaniac | stekern: Ahh that explains it, found your Github last night and just assumed you were Finnish thanks to what it says there. | 06:32 |
| olofk | Powermaniac: orpsoc is a tool to make it easier for me and others to quickly set up a system (presumably based on OpenRISC), run tests and generate FPGA images. | 06:35 |
| stekern | Powermaniac: I only use the de0 nano for development | 06:36 |
| Powermaniac | stekern: Oh, I thought you were using it as a sort of system with the lcd attached etc... | 06:37 |
| stekern | I do, but I don't really "use" it for something | 06:37 |
| Powermaniac | So it's more for testing to see it works, I assume | 06:38 |
| stekern | things aren't so interesting anymore when they work | 06:38 |
| olofk | stekern: That's terribly true :) | 06:39 |
| Powermaniac | So is my idea to use the ORPSoC as an as open source system as possible a realistic goal? Or well just ridiculous idea.../ | 06:40 |
| Powermaniac | ? | 06:40 |
| Powermaniac | Oh and do you guys know anything about if the OpenRISC ASIC will ever happen? | 06:40 |
| olofk | It's not a ridicilous idea, but it's still far away from reality | 06:40 |
| Powermaniac | Or ORPSoC ASIC not sure whether that is possible though | 06:41 |
| jeremybennett | Powermaniac: You can probably make it as open source as synthesizing to gates - there have been attempts at open source synthesis tools. | 06:43 |
| jeremybennett | But beyond that you are in the hands of the FPGA vendors. | 06:43 |
| Powermaniac | Ahh okay. | 06:44 |
| Powermaniac | Now I just wondering if I can get hold of a 4x usb port hub that connects via GPIO | 06:44 |
| jeremybennett | I haven't seen any news of the ORPSoC ASIC for a long time. I suspect it is going nowhere. It doesn't really make sense - OpenRISC works as an FPGA or in an application specific SOC, but as a standalone ASIC | 06:44 |
| Powermaniac | Or if there is someway to do that with the single usb port on the DE0 Nano | 06:44 |
| jeremybennett | Powermaniac: The DE0 Nano has a USB port, and IIRC it uses the FTDI chip, so you can simultaneously run serial through it if that is what you want. | 06:46 |
| jeremybennett | If you want a separate dedicated USB, then you'll need to drive some sort of USB adapter from a sub-set of the DE0-nano pins. | 06:46 |
| Powermaniac | jeremybennett: Well yeah I want to run 4 things through it, wifi, mouse, keyboard, hdd or microsd if possible... | 06:47 |
| Powermaniac | And then use the GPIO pins to connect a lcd like Stekern | 06:47 |
| ams | Emacs rebooted... | 06:50 |
| Powermaniac | I need to double check something with you guys | 06:54 |
| Powermaniac | Can the ORPSoC on the fpga send out a HDMI or DVI signal? | 06:54 |
| Powermaniac | To the 40 pin gpio or 26 pin header? | 06:54 |
| Powermaniac | Okay so I found this: http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=09049535992720993533&cid=09049605030737850288&id=0D220643369276606715 | 07:02 |
| Powermaniac | Which has 4x usb and a dvi connection for the 26 pin header | 07:02 |
| jeremybennett | Powermaniac: Something to ask the HW boys - I'm a SW person. | 07:02 |
| Powermaniac | Okay thanks | 07:03 |
| olofk | Powermaniac: You need a dedicated HDMI phy for that. The HDMI signals needs to be swiched at a GHz rate, but regular GPIO pins only switch at ~100MHz (there are other issues too). You should get a board with a built-in HDMI or DVI transceiver, or hook up your FPGA board to a daughter board with a PHY | 07:15 |
| olofk | Powermaniac: For you purposes, I think a Digilent Atlys, or the Cyclone board that you saw earlier would be a better fit | 07:16 |
| stekern | jeremybennett: you can't run serial through the USB port on de0 nano | 07:16 |
| stekern | that's why you have that breakout board with the nice logo on here: http://www.embecosm.com/2013/04/25/chip-hack-fpga-programming-for-beginners/ | 07:18 |
| stekern | Powermaniac: if I would be you, I'd go for that Cyclone V board you posted about | 07:20 |
| Powermaniac | olofk: Thanks for the answer you too stekern | 07:20 |
| Powermaniac | Okay just need one more usb port on that and then I'm set | 07:21 |
| olofk | jeremybennett: Couldn't you have a cookie on the embecosm site that remembers if you have chosen to accept cookies? I have to answer that every time | 07:21 |
| Powermaniac | Unless there is 4 usb ports can't tell really from the photo | 07:21 |
| stekern | we don't have an orpsoc board port for that, but that would be a good starting point for your experiments I think | 07:21 |
| Powermaniac | stekern: Okay now to find out the shipping costs O_O | 07:22 |
| olofk | Powermaniac: You got a uSD card on it already, so you don't need a separate USB for that | 07:22 |
| stekern | you could check if there are resellers for that board more close to you | 07:22 |
| Powermaniac | olofk: I don't? I need 3x usb ports, what exactly do you mean I don't need another 1 as there appears to only be x2 usb ports on this board: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=830&PartNo=1 | 07:24 |
| Powermaniac | stekern: Here, in Australia I can only hope but I doubt it | 07:24 |
| Powermaniac | stekern: Will try contacting Terasic anyway about it I guess | 07:25 |
| _franck_ | olofk: about orpsocv3, the next thing you (we) should focus on is make error more verbose | 07:25 |
| _franck_ | a backtrace is not that clear for normal users..... | 07:26 |
| _franck_ | but I know, we don't target normal users :) | 07:26 |
| stekern | Powermaniac: there's no USB *host* ports on that board | 07:26 |
| olofk | _franck_: I think I just catch all exceptions in the top level and print out "You suck! Try again!". Would that make things more clear? :) | 07:26 |
| olofk | No, but seriously, I've been trying to catch exceptions when I find them, so please report (or fix) any crashes with backtraces that you find | 07:27 |
| olofk | I also need to remove all the internal exit(1) if I ever want to have a GUI instead of the CLI | 07:28 |
| Powermaniac | olofk: realised I don't nede 3x usb ports, it has a microUSB port so that solves the storage problem | 07:28 |
| Powermaniac | microSD* | 07:29 |
| olofk | Oh.. and I will probably not be around that much the coming week or two. Moving into my house tomorrow! So please mail me if you want my attention | 07:29 |
| olofk | Or send a fax. I like fax | 07:29 |
| stekern | faxes are the best | 07:30 |
| stekern | we never had a real fax though, just a fax modem. | 07:31 |
| olofk | Me too. Time to get one | 07:31 |
| stekern | but my friend did, so when we needed picture in a document for school, we'd go to his house and fax the pictures to my computer | 07:31 |
| olofk | haha | 07:32 |
| _franck_ | olofk: you want a backtrace example ? just call orpsoc without any argument | 07:32 |
| olofk | _franck_: Hmm.. weird. I get the help when I do that | 07:34 |
| olofk | http://pastie.org/8348141 | 07:34 |
| _franck_ | ok, I'll try again | 07:34 |
| olofk | _franck_: I see that your OpenOCD patch is close to be applied now | 07:40 |
| _franck_ | yes, however there is something strange I need to clarify | 07:40 |
| stekern | I neither get any backtrace when running 'orpsoc' without arguments | 07:41 |
| _franck_ | openocd receive data in the right endianess then swap it before sending it to the adv_debug_if !? | 07:41 |
| stekern | where in openocd is that decision made? that it should be swapped | 07:42 |
| stekern | does openocd now anything about target endianess? | 07:43 |
| _franck_ | in target specific code | 07:43 |
| _franck_ | or1k.c | 07:43 |
| _franck_ | but it does work | 07:43 |
| _franck_ | I know adv_debug_if can be configured to work on big/little endian but the default config is big endian | 07:44 |
| _franck_ | I need to take a look a t this. However, yesterday night, autoconf didn't want to let me compile openocd.... | 07:45 |
| stekern | if it work, then the data can be in right endianess, can it? | 07:45 |
| stekern | let me rephrase that.. | 07:46 |
| _franck_ | olofk: http://pastie.org/8348157 | 07:46 |
| stekern | if it works when you swap it, how can the data be in right endianess when you receive it then? | 07:47 |
| olofk | _franck_: Ah. I see. Might be a python 3.3 problem. Haven't checked the compability there | 07:48 |
| _franck_ | stekern: I mean gdb send us data in the right endianess (until now I thought it was in host endianess). Then we change it to little endian before send it the the debug unit | 07:52 |
| _franck_ | then it works !? | 07:52 |
| stekern | aha, understood | 07:53 |
| mor1kx | [mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/f43340ea27954e1e64760489149538c8f7393db6 | 08:57 |
| mor1kx | mor1kx/master f43340e Stefan Kristiansson: import mor1kx_monitor from mor1kx-dev-env... | 08:57 |
| stekern | olofk: ^ happy? ;) | 08:58 |
| olofk | stekern: You're my favorite pusher | 09:01 |
| stekern | I know how to control my diila's | 09:05 |
| Powermaniac | Oh no I've got thinking again | 10:24 |
| stekern | oh oh | 10:46 |
| stekern | ;) | 10:46 |
| Powermaniac | #electronics just sort of blew that idea out of the water though | 10:46 |
| Powermaniac | Creating an open source FPGA out of TTL chips | 10:46 |
| Powermaniac | And then implementing ORPSoCv2 on it | 10:47 |
| Powermaniac | For more open sourceness | 10:47 |
| Powermaniac | But TTL chips are patented also | 10:47 |
| stekern | I assume you have a flight hangar to fit it? | 10:49 |
| stekern | and the wallet to power it? | 10:50 |
| Powermaniac | Yes totally...>_> | 10:50 |
| Powermaniac | This is supposedly 1 'part' of an FPGA http://blog.notdot.net/2012/10/Build-your-own-FPGA | 10:51 |
| stekern | yes, it's a 'slice' (or Logic Element (LE), terminology differs a bit depending on the source) | 10:55 |
| stekern | do you know how FPGAs are (usually) built up? | 10:55 |
| stekern | (hint: it's described in the link you pasted) ;) | 10:56 |
| ams | Powermaniac: huh? no they are not. | 10:57 |
| ams | and making a "FPGA" out of ttl's isn't that hard ... depending on things. | 10:59 |
| ams | not immensly expensive, powerwise of hardware-wise. | 11:00 |
| ams | you do might need to unplug your stove to power it.. | 11:00 |
| Powermaniac | ams: LOL | 11:01 |
| ams | and move your fridge and freezer ... | 11:03 |
| ams | but it isactually doable .. | 11:05 |
| ams | and not that horribly expensive | 11:05 |
| Powermaniac | So not that expensive, but huge and power hungry interesting... | 11:14 |
| ams | yup | 11:14 |
| ams | Powermaniac: think about it, machiens back in the day where ttl's ... | 11:14 |
| ams | Powermaniac: the pdp-8/s was 1000 transistors, and 2000 diodes | 11:15 |
| Powermaniac | There is a simulation for the OpenRISC 1200 right? Or is it for the ORPSoCv2? | 11:24 |
| Powermaniac | If so what can that simulation be used for? | 11:24 |
| stekern | ams: yes, but the pdp-8/s is a lot simpler machine than or1k | 12:03 |
| stekern | Powermaniac: yes, there are simulation environments to simulate the whole system (with or1200 or mor1kx) | 12:04 |
| ams | stekern: i suspect you could get a whole or1k in a 19" box based on ttls ... | 12:05 |
| ams | though i also suspect it is one of those "i'll belive you when i see it" situations :-) | 12:05 |
| stekern | ams: you might be right, I haven't really calculated on it | 12:06 |
| stekern | I think a fairly simple system is around 10k LE in altera terms | 12:07 |
| ams | stekern: and if you microcode most of it ... | 12:09 |
| stekern | so if you want to do it the "build an FPGA" way, and approximating it to two chips per LE (one flip-flop and the LUT) | 12:09 |
| ams | prolly even simpler | 12:09 |
| stekern | you get 20 000 chips | 12:09 |
| stekern | microcoding is cheating, the theory is around existing implementations atm ;) | 12:11 |
| stekern | so the question is, what's the smallest area you can fit those 20 000 chips on | 12:12 |
| stekern | and the result of that is still a round-downwards, since no interconnect logic is counted in that | 12:13 |
| Powermaniac | stekern: So you can simulate the whole system | 12:24 |
| Powermaniac | stekern: Is there a guide on doing this? | 12:24 |
| Powermaniac | As I am interested in trying it out | 12:24 |
| Powermaniac | Also what is the difference between the or1200 and the mor1kx? | 12:26 |
| stekern | mor1kx is cooler (bias alert) ;) | 12:26 |
| Powermaniac | Okay, going to assume you are mainly developing the mor1kx then. | 12:27 |
| stekern | ok, since we are moving towards orpsocv3 in fast pace, I should probably point you to that | 12:28 |
| Powermaniac | Okay sure | 12:28 |
| stekern | grab https://github.com/openrisc/orpsoc and https://github.com/openrisc/orpsoc-cores | 12:28 |
| Powermaniac | Wait will I need to be on linux for this? If so I will be right back and swap to Debian. | 12:29 |
| Powermaniac | ? | 12:29 |
| stekern | in orpsoc: ./configure && make && make install | 12:29 |
| Powermaniac | Debian it is as ./configure I've never seen/heard of being a command inside windows | 12:29 |
| Powermaniac | So be right back and hold that thought | 12:29 |
| stekern | yes, I don't think this have been tested on anything else than linux | 12:29 |
| powermaniac | Okay back! | 12:32 |
| powermaniac | So what did I need to grab? | 12:32 |
| stekern | https://github.com/openrisc/orpsoc and https://github.com/openrisc/orpsoc-cores | 12:33 |
| powermaniac | When you say grab you mean just clone it right? | 12:38 |
| stekern | yes | 12:38 |
| powermaniac | Going to grab it as a zip file | 12:41 |
| powermaniac | Didn't realise linux didn't have a client like Windows does =\ | 12:41 |
| powermaniac | Okay so that is done | 12:43 |
| stekern | "didn't have a client like windows"? | 12:45 |
| powermaniac | Oh Github for Windows: http://windows.github.com/ | 12:45 |
| stekern | ok, so in orpsoc: ./configure && make && make install | 12:46 |
| powermaniac | Hmm | 12:49 |
| powermaniac | So I'm in the orpsoc-master directory (I'm not root) and I'm getting from "./configure && make && make install" the response: "bash: ./configure: No such file or directory" | 12:50 |
| powermaniac | Just tried in the directory orpsoc and got the same | 12:51 |
| stekern | ah, sorry, you need to run 'autoreconf -i' first | 12:54 |
| stekern | and you probably need to run 'make install' as root | 12:54 |
| powermaniac | "autoreconf -i" is returning: "bash: autoreconf: command not found" | 12:56 |
| stekern | you probably need autoreconf then | 12:57 |
| powermaniac | Getting it | 12:59 |
| powermaniac | DONE! | 13:00 |
| powermaniac | Did ./configure && make && make install successfully | 13:01 |
| powermaniac | So now what do I do...? | 13:02 |
| stekern | make a new directory in the same directory as you have orpsoc-cores called build | 13:03 |
| powermaniac | orpsoc-cores-master? | 13:04 |
| stekern | create a file called orpsoc.conf with the following lines in it: | 13:04 |
| stekern | [main] | 13:04 |
| stekern | cores_root =../orpsoc-cores/cores | 13:04 |
| stekern | systems_root =../orpsoc-cores/systems | 13:04 |
| stekern | in the build directory | 13:05 |
| stekern | if your orpsoc-cores directory is called orpsoc-cores-master, adjust accordingly | 13:05 |
| powermaniac | Ahh okay | 13:05 |
| powermaniac | Okay done | 13:07 |
| stekern | download this file | 13:08 |
| stekern | http://oompa.chokladfabriken.org/openrisc/uart-simple.elf | 13:08 |
| powermaniac | Okay | 13:08 |
| powermaniac | Done | 13:08 |
| stekern | install iverilog | 13:09 |
| stekern | when that's done, in the 'build' directory run: | 13:10 |
| stekern | orpsoc sim or1200-generic --or1k-elf-load /path/to/uart-simple.elf | 13:10 |
| powermaniac | Seem to have gotten a few errors | 13:18 |
| powermaniac | http://pastebin.com/wp4eRKLT | 13:21 |
| powermaniac | Any ideas? | 13:27 |
| _franck_ | in Makefile.am, we miss orpsoc/provider/url.py | 13:29 |
| _franck_ | sorry about that, it's my fault | 13:31 |
| powermaniac | Oh okay, no problem | 13:31 |
| powermaniac | Can it be easily fixed? | 13:31 |
| _franck_ | look in https://github.com/openrisc/orpsoc/blob/master/Makefile.am#L19 | 13:31 |
| _franck_ | just add a line with orpsoc/provider/url.py | 13:32 |
| _franck_ | then configure and install orpsoc again | 13:32 |
| powermaniac | Okay cool thanks | 13:32 |
| powermaniac | I keep getting this error now when doing a ./configure && make && make install: Makefile:873: *** missing separator. Stop. | 13:43 |
| _franck_ | you may have forgot a "\" on the line before the one you inserted | 13:44 |
| stekern | powermaniac: look, you're already an openrisc contributor, finding bugs and all! \o/ | 13:47 |
| powermaniac | stekern: Yay! | 13:47 |
| powermaniac | Aha! I think I worked it out | 13:49 |
| powermaniac | Needed to change the makefile.am before autoreconf -i | 13:49 |
| powermaniac | New error: Error: Command svn not found. Make sure it is in $PATH | 13:52 |
| powermaniac | I thought svn was built in? | 13:52 |
| powermaniac | Okay tried again and now I get: "or1k_elf_loader: Unable to find a `or1k_elf_loader.vpi' module on the search path. orpsoc.elf: Unable to open input file. Error: Failed to run simulation" | 13:56 |
| stekern | oh, the elf-loader use or1k-elf-objcopy... | 14:12 |
| powermaniac | ? | 14:13 |
| stekern | it has a dependency on the or1k toolchain | 14:13 |
| stekern | so you'll need that | 14:13 |
| powermaniac | How do I get that then? | 14:13 |
| stekern | http://opencores.org/or1k/OpenRISC_GNU_tool_chain#Newlib_toolchain_.28or1k-elf.29 | 14:14 |
| powermaniac | Oh and thanks again for all the help | 14:14 |
| stekern | you probably want that anyways if you're going down and dirty with or1k ;) | 14:14 |
| stekern | I've got a little .bin loader for the arm on the sockit now | 14:15 |
| powermaniac | I might have to let this rest for tonight and come back to this tomorrow | 14:15 |
| powermaniac | To complete it on my computer anyway | 14:16 |
| stekern | I mean, a .bin loader that runs on the ARM, loading the binary into or1k memory | 14:16 |
| stekern | there's something off when loading Linux with it though, it shows no signs of life | 14:17 |
| powermaniac | I would say interesting but I'm not entirely sure the implciations of that | 14:17 |
| stekern | =) | 14:17 |
| powermaniac | Wait I shall swap over to my tablet so we can continue talking but I won't be able to go on with finishing implementing the ORPSoC for tonight anyway | 14:18 |
| powermaniac | So bye for a second | 14:18 |
| Powermaniac | And back | 14:19 |
| Powermaniac | So you were saying about this .bin loader, what exactly does it do? | 14:20 |
| Powermaniac | Is this something that could be combined with say the Epiphany 3 on the Parallella board? | 14:20 |
| Powermaniac | Wait no I mean the Zynq as it has an embed Arm processor on the fpga | 14:21 |
| stekern | I have an sockit dev board, which has an ARM processor alongside the FPGA | 14:22 |
| stekern | much like the zynq | 14:22 |
| stekern | and on that board there are 2 DDR3 memories, one for the ARM and one for openrisc (FPGA) | 14:23 |
| Powermaniac | Okay that is interesting | 14:24 |
| stekern | so what I'm doing is loading a binary file from the ARM into the openrisc memory and then reset the openrisc so it boots from what I have loaded into its memory | 14:24 |
| Powermaniac | So does that makes things easier? | 14:25 |
| Powermaniac | Very tempted to get the Parallella as it is far cheaper then that Cyclone V board I was looking at | 14:26 |
| Powermaniac | And it has all the ports I need | 14:26 |
| Powermaniac | Still have to wait for funds to come through e.g. parents getting paid... | 14:26 |
| Powermaniac | See considering I'm 18 I really should get a job but I also should really finish high school (bloody chaotic life). And now you know a bit more about me... | 14:29 |
| Powermaniac | Anyway...Yes the Parallella although Andrew Back said it probably wouldn't be suitable for what I want to use it for... | 14:35 |
| stekern | I'm not sure how the peripherals are connected on that board, on this board most are connected *only* to the ARM | 14:39 |
| stekern | exceptions are VGA and ac97 | 14:39 |
| stekern | so you can't access ethernet PHYs and sdcard from the FPGA for example | 14:41 |
| Powermaniac | Hmm okay shall try and pester the creator of Parallella on twitter or ask in the forums | 14:43 |
| Powermaniac | About what the FPGA is connected to | 14:46 |
| Powermaniac | What does the ORPSoC need in an FPGA, Ipsomething called LUTs or something | 14:50 |
| Powermaniac | Like there mist be a bare minimum requirement right? | 14:50 |
| stekern | ooh, it works if it's the first thing I load | 15:07 |
| Powermaniac | ? | 15:12 |
| Powermaniac | The .bin loader I assume | 15:13 |
| stekern | yes, loading Linux | 15:24 |
| mschulze | Hi! | 15:27 |
| Powermaniac | Hi mschulze | 15:30 |
| mschulze | Powermaniac: Do you have experience with the orpsoc version 2? | 15:33 |
| Powermaniac | Mschulze: Not exactly, was getting ORPSoCv3 up and running as a simulation today though | 15:34 |
| mschulze | Okay, I still have trouble with my stuff here, I am building a generator for the v2 bus arbiters and top level entity, I removed a lot of cores from the system I am building, but the build script still wants the configuration verilog files of the removed cores | 15:36 |
| mschulze | Any idea? | 15:37 |
| Powermaniac | Mschulze: What your doing seems way out of my league I'm very new to this | 15:41 |
| mschulze | I still feel very new after one year of digging into this all... :-D | 15:42 |
| stekern | mschulze: that's a defiency of orpsocv2, if the core is in the root rtl/verilog/ directory it will be used by all boards | 15:43 |
| stekern | if I understand your problem right | 15:43 |
| stekern | at least that was an answer to a question you asked a week or so ago about the vga core | 15:44 |
| mschulze | stekern: that makes no sense, the use of the core should be optional... | 15:44 |
| stekern | hence the word "deficiency" | 15:45 |
| stekern | well, the use of it is optional, but all of the files there will be compiled | 15:46 |
| mschulze | I have trouble getting into my generated system via the JTAG bridge and am wondering why the "standard" debug interface is overwriting the configuration of the adv_dbg_if | 15:46 |
| stekern | not much help for you now, but this all is handled *much* better in orpsocv3 | 15:47 |
| mschulze | For me it doesn't make sense to port a generater to v3 that isn't working in v2 | 15:49 |
| Powermaniac | Stekern: quickly I shall ask before you disappear again does it list anywhere the minimum requirements for orpsoc? | 15:50 |
| mschulze | Powermaniac: I would say "It depends", altough that will not the answer you are looking for. I use the de0-nano board from terasic and http://pastebin.com/YxHaU6hB there you can see the map summary. I don't know how much of the chip is actually used. | 16:07 |
| Powermaniac | mschulze: I was thinking of just comparing against the De0-nano but still not quite sure what I even need to be comparing so... | 16:09 |
| Powermaniac | Mschulze: See I'm looking at the parallella board which aphas a zynq 7010 FPGA onboard | 16:09 |
| mschulze | http://videos.fscons.org/fscons/videos/FSCONS2011/about-the-openrisc-project/slides.pdf there is mentioned that the system will need 4000 LUT and 7 BRAM for the processor. I don't know how if it's still valid. | 16:18 |
| mschulze | So it should fit in that zynk 7010 chip as it has over 17k LUT and 60 RAM blocks | 16:20 |
| mschulze | But do you really need one more processor on that board? ;-) | 16:21 |
| mschulze | I will go and take a walk now, need some wind in my head... Good luck. | 16:28 |
| -!- J-_2--- is now known as aaaaaaaaa | 19:24 | |
| mschulze | Hi! For all that read my previous questions: I figured out that I have a problem with the wishbone bus that is returning wrong crc checksums. I will need more time to fix that. Thank you for all comments. | 19:54 |
| ysionneau | for those interested: https://class.coursera.org/comparch-2012-001/class/index | 19:55 |
| ysionneau | free course about cpu design (computer architecture) | 19:56 |
| _franck_ | mschulze: are you working in simulation ? | 20:21 |
| mschulze | _franck_: No, I am working on "real hardware", the simulation doesn't work for me at the moment :-( | 20:26 |
| _franck_ | ok, I'm asking because I had problem with crc in simulation while reading uninitialize memory/registers | 20:29 |
| _franck_ | wich tap/debug unit combination are you using ? | 20:29 |
| mschulze | i am sure that my problem is in my generated files... | 20:30 |
| _franck_ | ah ok | 20:30 |
| mschulze | the altera_jtag_tap and the advanced debug interface | 20:30 |
| _franck_ | ok, this is a well tested config | 20:31 |
| mschulze | the board port residing under the boards/altera/de0_nano direcotry works perfectly for me, but my generated files based on that specific board doesn't work | 20:31 |
| mschulze | I got some CRC errors when I tried to connect the board with the adv_jtag_bridge, after appending the -t option it told me that the wishbone bus doesn't work... | 20:33 |
| _franck_ | if your software side works with the de0 port, you're right, it is somewhere in your hardware files | 20:35 |
| _franck_ | I was about to tell you to move to openocd, but don't change your test setup if it works with the de0 | 20:36 |
| mschulze | It works perfectly, I will sure move to openocd at some point but not now, it's two weeks befor the ORCONF and my stuff is not working... I am on vacation, tired of looking at my code and the verilog code. I won't change my setup now :-) | 20:39 |
| mschulze | Is there a way to simulate or test a wishbone bus implementation against it's specification? | 21:06 |
| --- Log closed Tue Sep 24 00:00:10 2013 | ||
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