| --- Log opened Sat Jun 15 00:00:44 2013 | ||
| stekern | I can't read the DRAM from the arm side neither, maybe it's not configured... | 02:54 |
|---|---|---|
| stekern | jupp, that seems to be it | 03:52 |
| stekern | after configuring it I can read the DRAM fine from the arm side at least | 03:52 |
| stekern | hno: the AR100 can access the DRAM | 03:56 |
| stekern | that's pretty cool | 03:57 |
| stekern | so I've got a nice little openrisc board here with a couple of arm co-processor cores ;) | 03:58 |
| hno | stekern, and 2GB of RAM (or is it 1GB?) | 05:27 |
| hno | but I guess it has no MMU on the OpenRISC side? | 05:28 |
| stekern | 2GB of RAM | 05:34 |
| stekern | no, unfortunately no MMU, otherwise we would be able to boot linux on it ;) | 05:34 |
| stekern | but it has icache (no dcache) | 05:35 |
| hno | so who is the first to port uClinux to openrisc? | 05:49 |
| stekern | that's of course an option | 06:06 |
| stekern | timer is working too | 06:35 |
| stekern | my crude clk freq detection method shows ~26 MHZ | 07:22 |
| stekern | so, it's probably running of the 24 MHz osc | 07:22 |
| stekern | +f | 07:29 |
| hno | stekern, clock can likely be changed. Haven't seen any hardcoded clock selections in Allwinner chips yet save for SATA and something else... | 08:53 |
| stekern | hno: ok, I'll dig into that some more, I still think my assumption that it runs off the 24 MHz osc as default is valid | 09:52 |
| stekern | another interesting thing is that it has l.addc support | 09:52 |
| stekern | and a hardware divider | 10:04 |
| stekern | hmm, and it has the mac unit bit set in UPR and l.mac *is* supported | 10:21 |
| stekern | so, this is the current test results: http://pastie.org/8046404 | 17:25 |
| stekern | ok, now I've got sun6i u-boot running over the sdcard serial, plan is to boot linux and get ar100 to print out it's stuff on this uart too | 19:26 |
| hno | sounds like a good plan. | 19:33 |
| --- Log closed Sun Jun 16 00:00:45 2013 | ||
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