| --- Log opened Sun Apr 28 00:00:34 2013 | ||
| stekern | juliusb: so like a prefetcher? | 02:20 |
|---|---|---|
| stekern | few-word caches is basically what I have in the SDRAM controller, one for each port, to hold a 1 burst length | 02:25 |
| stekern | (or was it 2 bursts perhaps) | 02:28 |
| stekern | anyways, from the testing I did when I wrote that, you get a really good speed up with a small cache like that alone | 02:29 |
| stekern | but otoh, if you now connect pronto to my sdram controller, you'll not notice much of a difference, since the few-word cache already is there | 02:30 |
| stekern | juliusb: I just tested running the kernel without the latched-level irq workaround, works fine | 02:59 |
| @juliusb | stekern: (interrupts) nice, which did you use - edge or level? | 10:20 |
| @juliusb | or do both work? | 10:20 |
| stekern | level | 11:08 |
| @juliusb | cool | 11:09 |
| @juliusb | as you've said before, these fetchers are not friendly are they? you have to spend a lot of time with them to talk them around to seeing things your way | 11:09 |
| @juliusb | one thing which has come to mind in all of this is whether a big monolithic state machine is what I want to do in future, instead of seemingly disparate state variables | 11:11 |
| @juliusb | would probably make it easier to debug and develop in future | 11:11 |
| @juliusb | because you have to remember what each signal means and is supposed to do when another signal does something | 11:11 |
| @juliusb | and when it's in a big state machine, it's a bit more obvious | 11:12 |
| stekern | you have to be a fetch whisperer to tame them, yes | 11:14 |
| @juliusb | :) | 11:14 |
| stekern | big state machines have their annoyances too, I tried to do that in the fetcher for a while too, but that bit me in the back end too | 11:15 |
| @juliusb | hmm, OK, having not done it I haven't had that experience | 11:16 |
| stekern | but the cappuccino fetcher is pretty non-statesy now | 11:23 |
| stekern | all external (non-cache-refill) bus-accesses have one cycle latency, where it is decided if the bus access is really allowed to start | 11:24 |
| stekern | and then the result is registered, thus saved if fetch happen to be stalled during the bus access | 11:25 |
| stekern | ... I still have a small statemachine in the fetcher, but that's just me having an unnatural attraction to statemachines | 11:26 |
| @juliusb | don't worry, I think it's natural to be attracted to state machines with HDL design | 11:32 |
| @juliusb | but doing something like this mini cache guy in pronto has brought out a few bugs in the pipeline control logic | 11:34 |
| @juliusb | which would probably have been found if it was hooked up to a slightly different bus | 11:34 |
| --- Log closed Mon Apr 29 00:00:36 2013 | ||
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