| blueCmd | stekern: also, I have 3 patches for gcc - they do not depend on eachother, but since I should change ChangeLog they will modify the same file. | 00:34 |
|---|---|---|
| blueCmd | do you want everything as one commit? | 00:34 |
| blueCmd | stekern: you got a bunch of pull requests. I haven't taken the time to set up a regression test env. yet, and I'm going to spain for a couple of weeks soon - thought I would submit the patches asap | 01:13 |
| -!- erant is now known as Erant | 02:26 | |
| Erant | So I've been playing around with minsoc on this Atlys board, and I'm running into the issue where every few synthesis runs the core (or maybe the WishBone mux?) doesn't work. I'll have changed something completely unrelated, but the adv_debug stuff will go: | 02:28 |
| Erant | *** Doing self-test *** | 02:28 |
| Erant | Stall or1k - or1k is not stalled! | 02:28 |
| Erant | Sometimes I'll be dead in the water, sometimes an entire make clean will fix it. | 02:28 |
| Erant | I've got timing constraints on all the clocks in the system too, so I'm unsure where this is coming from. | 02:29 |
| stekern | Erant: and no timing errors? | 05:24 |
| stekern | blueCmd: nice, thanks | 05:27 |
| stekern | re the uclibc target change, I think we agree on that it will be necessary, perhaps we should give people on the mailing lists (openrisc@lists.openrisc.net, openrisc@lists.opencores.org) a chance to comment on it first though | 05:30 |
| Erant | stekern: Nope. All constraints met | 05:47 |
| Erant | I'm going to go through the timing report again to see if I'm missing any generated clocks | 05:48 |
| Erant | But those should be derived from the system clock | 05:48 |
| stekern | surely sounds like an timing issue | 07:33 |
| stekern | I never tested to run minsoc on atlys and never adv_debug_sys with it neither | 07:34 |
| stekern | dmmu progress, or1200-mmu test now fails instead of just crashing ;) | 07:34 |
| stekern | haven't hooked up the pagefault exception yet, everything else should be pretty much connected | 07:35 |
| stekern | and the cache is PIPT for now, should be changed to be VIPT in the future | 07:36 |
| stekern | but for that I need to change the cache (changes that are needed anyways) | 07:37 |
| blueCmd | stekern: about that, i'm not receiving any confirmation request when trying to join the openrisc.net lists. the opencores one works though | 12:54 |
| blueCmd | hm, TLS will be fun to implement. some kernel stuff, some reloation stuff, gcc stuff and finally uclibc / eglibc stuff - the whole shabang :) | 15:05 |
| stekern | ;) | 15:41 |
| Erant | stekern: Oh yeah, it sounds like a timing issue. But unsure where it's coming from. I might just try overconstraining some stuff. | 19:27 |
| Erant | I've gotten all paranoid now, started blaming the hardware. | 19:29 |
| Erant | Even though it's very rarely the hardware. | 19:30 |
| Erant | Hmm. It may have been a misconfigured DCM | 21:53 |
| -!- Netsplit *.net <-> *.split quits: ams, Amadiro | 22:19 | |
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