| juliusb | hmm, would an instruction where you jump with a register plus an immediate be of use? | 01:01 |
|---|---|---|
| stekern | juliusb: I'm not sure but I have a feeling it could be useful for position independent code | 06:44 |
| stekern | juliusb: (drop sfne) for fp, I don't think you can, since lf.sfeq;bf != lf.sfne;bnf | 06:47 |
| stekern | since, (!qnan(a) && !qnan(b) && a == b) is not the same as !(!qnan(a) && !qnan(b) && a != b) | 06:52 |
| stekern | also, without it you will lose the ability to do not equal cmovs, i.e. r <= a != b ? x : y | 07:02 |
| stekern | scratch that last claim, I had clearly not woke up yet: r <= a != b ? x : y; can of course be transformed into r <= a == b ? y : x; | 09:14 |
| juliusb | stekern: how useful is cmov? | 12:35 |
| juliusb | at present I've not got it in my proposed ISA | 12:35 |
| juliusb | but i very much like the idea | 12:35 |
| juliusb | cmov doesn't work like you proposed, though | 12:37 |
| juliusb | it's | 12:37 |
| juliusb | x = (a==b) ? y : x; | 12:37 |
| juliusb | isn't it? | 12:37 |
| juliusb | so you can only optionally write over a reg | 12:37 |
| juliusb | maybe we do want some 3 reg version of cmov? | 12:37 |
| stekern | ah well, you can transform it to y = (a==b) ? y : x then | 12:39 |
| juliusb | yes, but only if you have the ability to specify 3 registers | 12:40 |
| juliusb | i thought it was just cmov rA, rB | 12:40 |
| juliusb | where rA = (flag) ? rB : rA | 12:40 |
| stekern | x = (a!=b) ? x : y; => y = (a==b) ? x : y; then | 12:43 |
| stekern | I don't see any reason not having cmovs | 12:44 |
| juliusb | sure, a 3reg cmov | 12:46 |
| juliusb | i'd like to try and have it as a 16-bit insn | 12:46 |
| stekern | what is a 3reg? | 12:46 |
| juliusb | 3 registers | 12:46 |
| juliusb | so you can specify rD, rA and rB | 12:47 |
| juliusb | as opposed to just rA and rB (where rD = rA) | 12:47 |
| juliusb | i think the existing one in or1k is the 2 register version | 12:47 |
| stekern | yes, that's of course nicer, but I don't know if it's strictly necessary | 12:47 |
| juliusb | i think it is if you only have sfeq | 12:47 |
| juliusb | but... you know what I've done, we don't even have sfeq | 12:47 |
| juliusb | i'm considering putting it back in | 12:47 |
| juliusb | at present i just had sflt,sfgt,sfle,sfge | 12:48 |
| stekern | I have no idea what you've done ;) | 12:48 |
| stekern | x = (a!=b) ? x : y; => y = (a==b) ? x : y; <= doesn't that work? | 12:48 |
| juliusb | then a jump-if-flag, jump-if-no-flag, but then jump-if-equal, jump-if-not-equal | 12:48 |
| juliusb | you need a way of testing equality | 12:48 |
| juliusb | at present I don't have that | 12:49 |
| juliusb | :) | 12:49 |
| stekern | ah, no sfeq even, yeah that might be a bit cheap :) | 12:49 |
| juliusb | but im thinking of putting it back in and dropping the jump-if-eq | 12:49 |
| juliusb | but jump-if-eq will be nice, because i have a 16-bit version which can skip over up to 8 insn | 12:49 |
| stekern | why do you continue with the flag stuff? | 12:50 |
| juliusb | because it's very nice to have the flag | 12:50 |
| juliusb | and not put it in a register | 12:50 |
| juliusb | I mean a GPR | 12:50 |
| juliusb | you get some bit of state for free | 12:50 |
| stekern | no, it's not nice | 12:50 |
| juliusb | basically, 16-bit insns are too small to specify the comparison plus 2 regs plus put a useful immediate in it | 12:51 |
| juliusb | using a state bit is beautiful, it saves you room in your jump/branch insn | 12:51 |
| juliusb | ARM do it al ot | 12:51 |
| juliusb | and I can see why, it really gives you a lot more room in your conditional insns | 12:52 |
| juliusb | so I thought, OK, for eq/ne then do it straight in the branch insn because you're likely to use those most | 12:52 |
| juliusb | so you save the sf then jump-if-flag duo and just have a single 16-bit insn | 12:52 |
| juliusb | i'll send you my scratchpad so fr | 12:53 |
| juliusb | so i've got a 6-bit opcode space | 12:57 |
| juliusb | so far i've used up to 0x38, meaning there's only 7 left | 12:58 |
| juliusb | :( | 12:58 |
| juliusb | and I haven't got much in there | 12:58 |
| stekern | yeah, but arm have those nice predicated instructions... | 12:59 |
| stekern | what's bugging me most with the flag in or1k is that there isn't a nice way to get hold of the value of the flag without doing a branch | 13:02 |
| juliusb | oh yeah | 13:02 |
| stekern | (especially not without a cmov) | 13:02 |
| stekern | so perhaps a cmov and cmovi to would be good to have if the flag-style is kept | 13:03 |
| juliusb | when do you want to know the flag value, though? | 13:04 |
| juliusb | how often does that come up? | 13:04 |
| stekern | between 12:30 and 13:00 every thursday | 13:04 |
| stekern | :) | 13:04 |
| juliusb | :) | 13:05 |
| stekern | nah, but we have discussed the cons with a flag earlier, one being that you only have one flag at your disposal, and if you don't have a way to "save-away" the flag other than branching, then you will be forced to branch (or at least do a branch decision) between every comparison | 13:13 |
| stekern | but I see pro too, especially with as small immediate space | 13:16 |
| stekern | +the | 13:16 |
| juliusb | im very tempted to just rip off the whole ARM many-flag-register | 13:17 |
| juliusb | and have like a set-flag*s* insn | 13:18 |
| juliusb | then we could have that in spr space and then just mfspr that register | 13:18 |
| juliusb | i was considering having a jump-if-bit-set insn, which worked on a value in a GPR | 13:21 |
| juliusb | or I guess, could work on a SPR | 13:21 |
| juliusb | so you do your set-flags, and then depending on which condition you want, select that bit | 13:21 |
| juliusb | but could also be used to branch-if-lessthan-zero on a value without doing the compare (just test the top bit of the register, if it's '1' then it's <0 ) | 13:22 |
| juliusb | and maybe that's the best way, allow you do to the set-flags insn, and redirect the output to either a GPR or the SPR | 13:23 |
| juliusb | and let the jump-if-bit-set insn select GPRs or the SPR | 13:23 |
| juliusb | GPRs or SPRs, even, perhaps | 13:23 |
| stekern | SPRs aren't really compilerfriendly though | 13:28 |
| juliusb | sure, could be useful for assembly function writing though | 13:29 |
| stekern | it's hard to get them grasp what is going on in them other than "it touches the SPR, so you have restrictions on what you can do with it" | 13:29 |
| juliusb | sure, but it'd still be easy enough to give it the concept of "this insn will be testing against bits in an SPR, which you don't have to worry your pretty little head about" | 13:32 |
| stekern | sure, but you have the problem that "this insn will modify bits in that SPR, so you better not do anything else that might modify it" | 13:33 |
| stekern | you could probably model it per bit access though | 13:34 |
| stekern | what is the ARM many-flag-register called? | 13:34 |
| juliusb | CPSR? | 13:36 |
| juliusb | yeah I think it's the CPSR: Current Program Status Register | 13:37 |
| stekern | I presume the three reg version for j(n)eq is for jump to reg? | 14:10 |
| stekern | what are the benefits of having seperate sts instructions? | 14:12 |
| stekern | juliusb: wouldn't jnz rX, imm and jz rX, imm make more sense than jeq and jneq? | 14:32 |
| stekern | we could have both of course | 14:32 |
| stekern | btw, why are we aiming for a 32-bit _or_ 16-bit and not a mixed 16-bit/32-bit arch? | 14:47 |
| stekern | hmm, what is it that you have on sheet 1? | 14:51 |
| stekern | or1k cmov is 3reg btw | 15:40 |
| juliusb | I am aiming at mixed | 16:54 |
| juliusb | mixed is the way man, the only way :) | 16:54 |
| juliusb | get back to you other qs in a little while | 16:54 |
| stekern | yeah, I think _I_ got mixed up there for a while ;) | 17:31 |
| stekern | I was more thinking blackfin mixed though | 17:31 |
| stekern | only instructions that don't need 32 bit space are 16-bit | 17:33 |
| stekern | I think I've got the fp comparisons worked out now at least (and with cmov as well) | 18:16 |
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