| Flea86 | o/ | 00:55 |
|---|---|---|
| -!- Flea86 is now known as flea86|away | 03:02 | |
| -!- flea86|away is now known as flea86|soldering | 03:35 | |
| -!- flea86|soldering is now known as flea86|away | 04:00 | |
| Lampus|2 | Hello | 09:28 |
| flea86 | o/ | 09:28 |
| flea86 | Just curious, but is there a *complete* list of all the asic chips available that contain an openrisc core? | 09:29 |
| Lampus|2 | Hm.. I'm interesting in such list too | 09:30 |
| flea86 | Don't know if the other folks here are aware of this, but there's an appotech SOC that contains an openrisc core! XD | 09:31 |
| flea86 | 100MIPS of open-source asic goodness :P | 09:32 |
| Lampus|2 | What tech process has been used by appotech? | 09:37 |
| Flea86_ | got disconnected :S | 09:37 |
| Lampus|2 | Flea86_: What tech process has been used by appotech? | 09:38 |
| Flea86_ | Lampus: Good question! I've never asked them tbh | 09:39 |
| -!- Flea86_ is now known as Flea86 | 09:39 | |
| Lampus|2 | Flea86: do you talk about this chip: http://www.appotech.com/dp/product/apg301 ? | 09:40 |
| Flea86 | Lampus|2: No, but I suspect that it too is openrisc :3 | 09:41 |
| Lampus|2 | According to line "Input Voltage: 1.6-2.0" I can suggest that they used 0.18um tech process | 09:41 |
| Flea86 | http://www.appotech.com/dp/sites/default/files/factsheet/ax3008-fl-204-en_1.pdf | 09:42 |
| Flea86 | funny, that used to say *openrisc* | 09:43 |
| Flea86 | brb | 09:43 |
| Flea86 | back | 10:10 |
| Flea86 | :) | 10:10 |
| stekern | 3 | 11:58 |
| stekern | oops | 11:58 |
| Lampus|2 | I have a new problem. I have replaced onchip_ram to wishbone SDRAM controller. | 12:16 |
| Lampus|2 | adv_jtag_bridge Self-test PASSED successfully | 12:17 |
| Flea86 | I wish I could help you there Lampus|2, but I don't do any fpga stuff at this time.. :( | 12:18 |
| Lampus|2 | But when I trying to start 'hello world ' program, CPU is freezing | 12:19 |
| stekern | Lampus|2: how are you loading the program? | 12:22 |
| Flea86 | Lampus|2: What is your sdram frequency? have you tried just reading/writing data to/from the sdram? | 12:22 |
| Lampus|2 | stekern: using gdb with 'load' command | 12:22 |
| Lampus|2 | Flea86: I tried several frequencies. For now it's 50 MHz for wb_clk and sdram_clk | 12:23 |
| Lampus|2 | *have tried | 12:24 |
| stekern | you had it working with the onchip ram? | 12:25 |
| Lampus|2 | $ adv_jtag_bridge -a 1 -l 0:10 -l 1:4 -t usbblaster | 12:25 |
| Lampus|2 | Found Altera USB-Blaster | 12:25 |
| Lampus|2 | Found Altera USB-Blaster | 12:25 |
| Lampus|2 | firmware version = 0x0004 (4) | 12:25 |
| Lampus|2 | Enumerating JTAG chain... | 12:25 |
| Flea86 | stekern: He did | 12:26 |
| Lampus|2 | Hm. I was dropped from IRC. Seems this IRC server don't like very long messages =) | 12:27 |
| stekern | pastebin loves long messages ;) | 12:27 |
| Lampus|2 | stekern: yeah, I know. One second, please | 12:28 |
| Lampus|2 | http://pastebin.com/4ruavSJm | 12:29 |
| Lampus|2 | With onchip_ram all worked fine | 12:31 |
| stekern | what sdram controller are you using?= | 12:33 |
| Lampus|2 | After interrupting 'continue' command I have 'Remote failure reply: E01' error message | 12:33 |
| Lampus|2 | http://opencores.org/project,sdr_ctrl | 12:34 |
| Lampus|2 | And in adv_jtag_bridge output: ""Error while reading all registers: 'CRC mismatch' | 12:34 |
| Lampus|2 | CRC ERROR! Computed 0xb792881a, read CRC 0x1846ef33 | 12:34 |
| Lampus|2 | Retry count exceeded! Abort! | 12:34 |
| Lampus|2 | 12:34 | |
| Lampus|2 | Error while reading all registers: 'CRC mismatch' | 12:34 |
| Lampus|2 | Any ideas? | 12:38 |
| Flea86 | buy an openrisc asic? :P | 12:41 |
| * Flea86 runs | 12:42 | |
| Lampus|2 | It's not very good idea | 12:42 |
| Lampus|2 | I need my own ASIC =) | 12:43 |
| Lampus|2 | based on OpenRISC, of course =) | 12:44 |
| Flea86 | }:) | 12:45 |
| stekern | what sdram controller are you using? | 12:46 |
| Lampus|2 | stekern: as I have already said before http://opencores.org/project,sdr_ctrl | 12:47 |
| stekern | ah, sorry I missed that line :) | 12:49 |
| Flea86 | stekern: I always thought that any module that was truly 'wishbone compliant' just worked and that's it, right? | 12:51 |
| Lampus|2 | I have terasic DE0 board with Zentel SDR SDRAM 64Mbit with data width 16 bit, 12 bit row addr, 8 bit column addr, 4 banks | 12:52 |
| Flea86 | physical hardware considerations aside, ofc :3 | 12:52 |
| stekern | Flea86: yes, it should just work | 12:53 |
| stekern | of course, it could lack support of some features such as bursting etc | 12:53 |
| Flea86 | Lampus|2: I have similar (tmtech/etron) sdram chips on my flea86 hardware.. :) | 12:54 |
| Lampus|2 | But as I can see writing/reading of memory just works, and self-test passsed, but I can't run any program on it | 12:54 |
| Flea86 | Lampus|2: does the sdram controller also support burst modes as well? | 12:55 |
| stekern | Lampus|2: have you double checked your ibus connections? | 12:55 |
| Lampus|2 | Flea86: how I can test it? | 12:56 |
| Flea86 | openrisc also has a cache buffer, no? | 12:56 |
| Lampus|2 | Flea86: do you mean data/instruction cache? | 12:57 |
| Flea86 | Lampus|2: How, by running it in the expected (multiple?) sdram burst modes | 12:57 |
| Flea86 | Lampus|2: Yes | 12:57 |
| Flea86 | and performing 'block moves' of the sdram data, perhaps the Zentel parts require a specific setup? (never used them myself, but suspect they should just work) | 12:58 |
| Lampus|2 | `define OR1200_DC_1W_8KB | 12:59 |
| Lampus|2 | Oops | 12:59 |
| Lampus|2 | It's for ASIC | 12:59 |
| Flea86 | Lampus|2: huh? | 12:59 |
| Lampus|2 | `define OR1200_NO_DC | 12:59 |
| Lampus|2 | So I don't have data/instruction caches | 13:00 |
| Flea86 | stekern: Ah! try that now!! | 13:01 |
| Flea86 | }:A | 13:01 |
| * abogani waves all | 13:01 | |
| Flea86 | one less variable in the equation :) | 13:01 |
| abogani | Could anyone suggest me a cheap FPGA board which is capable of running Linux (on OpenRISC obviously)? | 13:01 |
| abogani | Thanks in advance! | 13:01 |
| Flea86 | Hey abogani o/ | 13:04 |
| Flea86 | Wish I could help, but fpga's aren't exactly my strongpoint personally.. | 13:05 |
| stekern | Lampus|2: you shouldn't need to enable caches to get things rolling | 13:05 |
| Flea86 | stekern: did you mean disable there? | 13:06 |
| Lampus|2 | But caches are already disabled | 13:06 |
| stekern | Flea86: the wb-bursting should not be connected to the bursting of the sdram-controller, and it should work even if the sdram-controller didn't support wb-burst modes | 13:06 |
| stekern | no, I meant enable, it should work with a no-dc setup too | 13:07 |
| abogani | Flea86: Thanks anyway :-) | 13:09 |
| Lampus|2 | My SDRAM controller connection: http://pastebin.com/bVhENHYs | 13:09 |
| Lampus|2 | Any comments? | 13:10 |
| Flea86 | brb | 13:10 |
| stekern | Lampus|2: not much to comment when not knowing what those are connected to | 13:18 |
| Lampus|2 | stekern: wb_ss_* - wires that were used before for onchip_ram. It's just default minsoc configuration in other parts | 13:20 |
| stekern | aha, ok, not that familiar with minsoc | 13:25 |
| Lampus|2 | stekern: Flea86: WB SDRAM controller that I'm using have wb_cti_i input (cycle type identifier), and I haven't connected it to something. Could it be source of problem? | 15:00 |
| Lampus|2 | What about compability between different revisions of wishbone? | 15:01 |
| Flea86 | Lampus|2: If that's an input to the sdram controller (wb_cti_i) then yes it could :) | 15:02 |
| Flea86 | just like in real hardware, you need to define *all* input states (though in this case the compiler might be already doing it for you, but don't count on it) | 15:05 |
| stekern | Lampus|2: have you looked at the sdram controllers code if it's used? | 15:06 |
| stekern | (afaict it's not) | 15:06 |
| Lampus|2 | Hm | 15:06 |
| Lampus|2 | stekern: strange, but seems that wb_cti_i in sdram controller not used anywhere | 15:09 |
| Lampus|2 | It's just declred as input in wb2sdrc module, but not used. | 15:11 |
| juliusb | that appotech SoC looks very interesting | 18:27 |
| juliusb | that may well be OpenRISC - I'd believe it | 18:27 |
| juliusb | all the specs look right for the processor | 18:27 |
| juliusb | although, there's programmable priority | 18:28 |
| juliusb | not sure OR1K has that | 18:28 |
| stekern | http://www.google.fi/url?sa=t&rct=j&q=appotech%20openrisc&source=web&cd=1&ved=0CCEQFjAA&url=http%3A%2F%2Fwww.appotech.com%2Fdp%2Fsites%2Fdefault%2Ffiles%2Fspec%2Fax3005-sp-112-en.pdf&ei=ba9LT9GHEK354QTm14zqAw&usg=AFQjCNE7ru9z6babqUjm52lZN7z21-eaUQ&cad=rja | 18:30 |
| stekern | bah | 18:30 |
| juliusb | google cache hey? | 18:32 |
| juliusb | is loading slowly for me | 18:32 |
| stekern | why can't you easily get the direct link to the pdf easily from google? | 18:32 |
| stekern | anyways, that pdf says openrisc, it's ax3005 | 18:33 |
| juliusb | oh yes indeed | 18:34 |
| juliusb | tick timer register is the same It hink | 18:35 |
| stekern | would be fun to play with one of those | 18:36 |
| juliusb | it would indeeed | 18:36 |
| juliusb | :) | 18:36 |
| juliusb | it's from a couple of years ago | 18:37 |
| juliusb | so if it's 100 MIPS probably running at 100MHz then | 18:38 |
| juliusb | assuming roughly 1-clock per instructino for most instructions | 18:39 |
| juliusb | or maybe a little more, say 120 MHz | 18:39 |
| juliusb | the PLL runs from 48-150MHz | 18:40 |
| juliusb | so maybe you can get it to 150MHz | 18:40 |
| juliusb | so if they've stuck with same RISC processor, they have a few other chips with it in, too | 18:42 |
| stekern | yeah, I'd guess the one flea86 posted probably has it too | 18:43 |
| juliusb | I contacted them asking for where we might buy them in europe or if they can mention any products containing them hehe | 18:49 |
| juliusb | we'll see what response I get | 18:49 |
| stekern | heh, cool. they are fairly recent at least | 18:56 |
| stekern | http://www.made-in-china.com/showroom/shunhua1117/offer-detailrqQmXESKJIhY/Sell-IC-Chip-for-Speaker-AX3008-.html | 18:58 |
| juliusb | I think this is talking about a dev board which has the AX2008 on it: http://translate.googleusercontent.com/translate_c?hl=en&ie=UTF8&prev=_t&rurl=translate.google.com&sl=zh-CN&tl=en&twu=1&u=http://download.ourdev.cn/bbs_upload587234/files_25/ourdev_530730.pdf&usg=ALkJrhiPsviC3-fLIuNaAWLx--WULIhzKg | 18:59 |
| stekern | http://www.diytrade.com/china/4/products/8199897/MP3_WMA_Decoding_chip_AX3008.html | 19:01 |
| stekern | min order 2500 | 19:01 |
| juliusb | haha: "The company doing the chip, but very clever to avoid the patent. Now basically use the open source IP, such as IEEE802.3, USB 2.0, open RISC." from here: http://translate.google.com/translate?hl=en&sl=zh-CN&u=http://diybbs.it168.com/thread-428077-1-1.html&ei=PbVLT5zBLsaw8gPoqcinDg&sa=X&oi=translate&ct=result&resnum=5&ved=0CEYQ7gEwBA&prev=/search%3Fq%3Dappotech%2Bopenrisc%26hl%3Den%26safe%3Dactive%26prmd%3Dimvns | 19:02 |
| juliusb | surely we could ask for some engineering samples | 19:02 |
| juliusb | no mention of MMU or using Linux on it | 19:02 |
| juliusb | Not sure google translate is correctly following the nuances of the language: "Taiwan's IC. Forget the development of electronic cockroach life all day is play of magical rotten tricks" | 19:06 |
| stekern | haha | 19:07 |
| juliusb | http://www.tomorrowelectronics.com/product-28473/Auto-MP3-AX3005.htm | 19:08 |
| stekern | reminds of that old jeremy clarkson show where he goes to some tuning shop in japan | 19:09 |
| juliusb | they could very well have bought this from beyond semiconductor, too | 19:09 |
| stekern | +me | 19:09 |
| stekern | they had just put all kinds of flashy english words on the rims | 19:10 |
| stekern | http://www.youtube.com/watch?v=7eDz1EkIB0Q | 19:10 |
| juliusb | haha, "All over the physical ironic power" | 19:13 |
| --- Log closed Mon Feb 27 22:16:09 2012 | ||
| --- Log opened Mon Feb 27 23:24:39 2012 | ||
| -!- Irssi: #openrisc: Total of 15 nicks [0 ops, 0 halfops, 0 voices, 15 normal] | 23:24 | |
| -!- Irssi: Join to #openrisc was synced in 1 secs | 23:24 | |
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